一種靜態隨機存取記憶體之感應放大器輸入訊號分析量測單元

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研究生：	盛以明 Yi-Ming Sheng
論文名稱：	一種靜態隨機存取記憶體之感應放大器輸入訊號分析量測單元 A Measurement Unit for Input Signal Analysis of SRAM’s Sense Amplifier
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	47
中文關鍵詞：	靜態隨機存取記憶體、量測、取樣、緩衝、放大器、可靠度、偏移、感應、測試、輸入訊號
外文關鍵詞：	SRAM, measurement, sampling, buffer, amplifier, reliability, variation, sense, test, input signal
相關次數：	點閱：3 下載：0
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傳統記憶體測試技術上大部分採取數位觀點與方法進行測試，較成熟的方法乃利用內建自我測試(BIST)、掃描鏈(Scan Chain)等方法針對記憶體系統各電路區塊進行功能測試，將輸入資料與輸出資料來做驗證，但是在感應放大器(Sense Amplifier)的部份卻是類比的行為。當記憶體做讀取動作時，在感應放大器致能的時間點位元線對(Bit Line Pair)上的電壓差是否足以讓感應放大器放大成正確的邏輯資料值是無法由數位的方法測試出來。
我的研究方向即是提出一種方法，能夠將感應放大器致能時的輸入訊號差取樣、放大，並將結果輸出以分析找出瀕臨臨界值的記憶體單元。也就是在感應放大器致能時間點取樣並鎖住電壓訊號，經過緩衝電路做電壓位準轉換且提供足夠驅動能力去驅動減法電路將取樣的電壓放大輸出以提高鑑別率，試圖用此方式找出一些因製程漂移所造成反應訊號較微弱之記憶體單元。由於此架構為內建式量測單元，故在設計上必須考量面積因素，以避免造成系統的額外負擔；此外，為節省量測時間，量測單元之操作速度也是重要考量因素之一。
藉由量測單元所輸出之量測結果除了可分析在任何製程技術下記憶體單元因為製程漂移導致反映出來之電壓訊號偏差情形外，更提供記憶體系統設計者一個修正並健全系統設計的方法，提高產品良率及可靠度。

A Static Random Access Memory (SRAM) measurement unit is presented to sample the voltage signals of bit line pairs and to amplify the weak signal to higher voltage differential level. According to the measured result, the reliability analysis can be easily completed through curve fitting process. The proposed circuit is designed and simulated with a 1K-bit SRAM by using the UMC 0.18μm 1P6M CMOS process. The analyzed result can provide designers to verify/strengthen their memory circuit design.

                         Contents
Abstract .............................................. 1
Contents .............................................. 2
List of Figures ....................................... 5
List of Tables ........................................ 7
Chapter 1 Introductions ............................... 8
1   Variation Issues .............................. 8
2   Previous Works ............................... 10
3   Organization ................................. 14
Chapter 2 Background ................................. 15
1   Traditional Test Technique on SRAM ........... 15
2   Motivation ....................................16
Chapter 3 The Proposed Measuring Architecture of SRAM ................................................. 18
1   Memory Array ................................. 18
1.1  Resistive Model .......................... 19
1.2  Capacitive Model ......................... 20
1.3  Total Parasitical Effects ................ 21
2   Sample and Hold Circuit ...................... 21
2.1  Sampling Switch .......................... 22
2.2  Differential Sampling .................... 22
2.3  Dummy Transistors ........................ 23
2.4  Delay Chains ............................. 26
3   Voltage Buffer ............................... 27
3.1  Level Shifter ............................ 27
3.2  Unit-Gain Buffer ......................... 28
4   Voltage Subtractor ........................... 28
4.1  Non-Ideal Term ........................... 29
4.2  Resistor Sizing .......................... 30
5   Sampling Methodology ......................... 32
5.1  Pass Transistor Switching ................ 32
5.2  Active Sampling .......................... 34
Chapter 4 Simulation Results and Comparisons ......... 36
1   Simulation Methodology ....................... 36
2   Simulation Result ............................ 39
2.1  Signal Distribution ...................... 39
2.2  Comparisons .............................. 41
3   Circuit Layout ............................... 43
3.1  Layout of SRAM Cell ...................... 43
3.2  Symmetry of Layout Geometry .............. 43
3.3  The comparison of Area ................... 44
Chapter 5 Discussions and Conclusions ................ 46
1   Discussions .................................. 46
2   Conclusions .................................. 46
Bibliography ......................................... 47

                                

Bibliography
[1] L. Ternullo, et al., “Deterministic self-test of a high-speed embedded memory and logic processor subsystem,” ITC, 1995, pp. 33-44,.
[2] R. Chandramouli, S. Pateras, “Testing systems on a chip,” IEEE Spectrum, Nov. 11 1996, pp. 42-7.
[3] R.D Adams, E.S Cooley, and P.R Hansen, “A self-test circuit for evaluating memory sense-amplifier signal,” Test Conference, 1997 Proceedings., International , 1-6 Nov. 1997, pp. 217 – 225.
[4] D.G Laurent, “Sense amplifier signal margins and process sensitivities,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 49, Mar 2002, pp. 269-275.
[5] R. Kraus and K. Hoffman, “Optimized sensing scheme of DRAMs,” IEEE. J Solid-State Circuits, vol. 24, Aug. 1989, pp. 895-899.
[6] R. Kraus, “Analysis and reduction of sense-amplifier offset,” IEEE J. Solid-State Circuits, vol. 24, Aug. 1989, pp. 1028-1033.
[7] Y.C Hsu, S.K Gupta, “An automatic test pattern generator for at-speed robust path delay testing”, Asian Test Symposium, Dec. 1998, pp. 88-85.
[8] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-hill, NY, International Edition 2001, pp. 418-423.

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