簡易檢索 / 詳目顯示

研究生: 潘瑞彧
Jui-yu Pan
論文名稱: 高介電係數材料作為閘極介電層之次微米金氧半元件特性及其電漿充電效應研究
Characteristics and Plasma Charge Effects on Sub-micron MOSFET Devices with Gate Dielectrics Using High-k Material
指導教授: 張廖貴術
Kuei-Shu Chang-Liao
口試委員:
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2002
畢業學年度: 90
語文別: 中文
論文頁數: 119
中文關鍵詞: 氮化矽氧化鉭高介電係數電漿充電效應
外文關鍵詞: Si3N4, Ta2O5, high-k, plasma charging effect
相關次數: 點閱:3下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文中,我們研究了兩種高介電係數材料作為閘極介電層元件的特性及其可靠性。
    在Si3N4元件方面,我們利用兩階段快速熱氧化閘氮化矽層的方式製備電晶體元件來探討元件的初始特性及可靠度分析,並且藉由光罩設計來探討電漿蝕刻時對元件所引發傷害之影響。氮化矽層在經過850℃,15秒作為第一階段快速熱處理後,再以800℃,15秒作為第二階段熱氧化處理之元件,在電晶體之最大轉導退化、臨界電壓漂移量及電漿充電傷害皆可有效地改善。

    在Ta2O5元件方面,我們嘗試不同的沈積前表面氮化處理溫度及沈積後退火處理(PDA)的方式製備電容元件來探討元件的初始特性及可靠性。我們發現沈積前表面氮化處理溫度為900℃,20秒搭配沈積後O2 Plasma退火處理的元件,其漏電流特性、崩潰電場可靠性、SILC的可靠性皆有所提升。


    第一章 序論…………………………………………..1 1.1 前言……………………………………………..……….1 1.2 研究動機…………………………………………...……2 1.3 高介電係數材料的選擇…………………………......….3 1.3.1 氮化矽(Silicon Nitride,Si3N4)的選擇…………………...…..3 1.3.2 氧化鉭(Tantalum Pentoxide,Ta2O5)的選擇……………...….5 1.4 氧化氮化層改善元件特性的機制……………………...7 1.4.1 RTP通N2O氧化氮化層之反應機制……………………….....7 1.4.2 Ta2O5的保護層…………………………………………….…..9 1.5 論文概要………………………………………..……….9 第二章 元件製程與量測…………………………..…13 2.1 Si3N4 NMOSFET 元件製程………………………...….13 2.1.1 晶片刻號及零層(Alignment Mark)曝光………………...…13 2.1.2 定義主動區(Active Region)………………………………..14 2.1.3 閘介電層(Gate Dielectric)的成長及退火處理………….....15 2.1.4 多晶矽閘極(Poly-Silicon Gate)的形成………………….....16 2.1.5 源極(Source)、汲極(Drain)、基極(Base)的形成……….…17 2.1.6 形成接觸窗(Contact Hole)、接出金屬線、燒結…………....18 2.2 Ta2O5 MOS-C元件製程…………………………...…..19 2.2.1 晶片刻號及零層(Alignment Mark)曝光………………….19 2.2.2 定義主動區(Active Region)………………………………..20 2.2.3 閘介電層(Gate Dielectric)的沈積及退火處理…….....….20 2.2.4 接出金屬導線及背鍍金屬……………………………….…21 2.3 電性量測……………………………………………..22 2.3.1 熱載子注入應力量測(Drain Avalanche Hot Carrier Stress)………………………………………………………………22 2.3.2 電容的量測…………………………………………….….23 2.4 材料分析…………………………………………….…24 第三章 以快速熱氧化閘氮化層之次微米MOS電晶體 元件特性與可靠度探討……..………………30 3.1 研究動機與目的…………………………………….…30 3.2 測試元件製程………………………………..………...32 3.3 結果與討論…………………………………..…..…...33 3.3.1 NMOSFET元件之初始特性…………………………..….…33 3.3.2 NMOSFET元件抗熱載子注入之特性……...………………36 3.3.3 材料分析………………………………………………....….38 3.3.4 漏電流的特性………………………………………….……39 3.3.5 崩潰電場的可靠性………………………………………… 41 3.4 結論…………………………………………………….42 第四章 以快速熱氧化閘氮化矽層以抑制次微米MOS 電晶體元件電漿蝕刻所造成之傷害…....…..65 4.1 研究動機…………………………………………….…65 4.2 研究目的……………………………………………….68 4.3 實驗方法…………………………………………….…68 4.3.1 電晶體佈局之設計……………………………………….....68 4.3.2 測試元件製程…………………………………………….....69 4.3.3 元件量測方法…………………………………………….....70 4.4 實驗結果與討論…………………………………….....72 4.4.1 固定天線面積下天線邊長對充電效應的關連性…………72 4.4.2 固定天線邊長下天線面積對充電效應的關連性……….....73 4.4.3 兩階段快速熱處理氮化矽介電曾與充電效應的相關性….74 4.5 結論…………………………………………………….76 第五章 以不同快速熱處理作表面氮化搭配沈積後退 火處理改善以Ta2O5為閘介電層元件特性之研 究…………………………...……………….88 5.1 研究動機及方法………………………….....………..88 5.2 實驗方法…………………………………………...…90 5.2.1 介電係數及等效厚度的比較………………………...........90 5.2.2 測試元件製程…………………………………………...…91 5.3實驗結果與討論……………………………………….93 5.3.1 電容電壓(CV)、介電係數、等效厚度特性分析…………..93 5.3.2 平帶電壓的比較…………………………………………...94 5.3.3 漏電流的特性(Gate Leakage Current Characteristic)….…95 5.3.4 崩潰電場可靠性的探討…………………………………..97 5.3.5 SILC(Stress Induce Leakage Current)的可靠性探………...98 5.3.6 材料分析…………………………………………………...99 5.4 結論…………………………………………………..100 第六章 結論與未來工作建議……………………....113 6.1 結論………………..……………………….....………113 6.1.1 Si3N4元件….……………………………………….113 6.1.2 Ta2O5元件….……………………………………….114 6.2 未來工作建議……..……………………….....………115 參考文獻…………………………………………..…116

    [1] C. Ho, “Gate Oxide Scaling Limits and Projection,” IEDM’96., pp. 319-322.
    [2] C. C. Chen, C. Y. Chang, C. H. Chien, T. Y. Huang, H. C. Lin and M. S. Liang, “Temperature-Accelerated Dielectric Breakdown in Ultrathin Gate Oxides,” Appl. Phys. Lett., vol. 74, pp. 3708-3710, 1999.
    [3] C. G. Parker, “Ultrathin Oxide-Nitride Gate Dielectric MOSFET’s,” IEEE Electron Device Lett., vol. 19, pp. 106-108, April 1998.
    [4] The National Technology Roadmap for Semiconductors Technology Needs, 1997 edition, Semiconductor Industry Association.
    [5] T. P. Ma, “Making Silicon Nitride a Viable Gate Dielectric,” IEEE Trans. Electron Devices, vol. 45, pp. 680-690, March 1998.
    [6] Ching-Wu Wang, “A Study of Ta2O5 High Dielectric Capacitors Fabricated by RF Magnetron Sputtering Method,” IEDMS’98., AP-22, pp. 219-222.
    [7] H. H. Tseng, “Application of JVD Nitride Gate Dielectric to a 0.35 Micro CMOS Process for Reduction of Gate Leakage Current and Boron Penetration,” IEDM’97., pp. 647-650.
    [8] B. Y. Kim, H. F. Luan and D. L. Kwong, “Ultra Thin (<3nm) High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In-Situ Rapid Thermal Processing,” IEDM’97., pp. 463-466.
    [9] S. C. Song, H. F. Luan, Y. Y. Chen, M. Gardner, J. Fulford, M. Allen, “Ultra Thin (<20Å) CVD Si3N4 Gate Dielectric for Deep-Sub-Micron CMOS Devices,” IEDM’98., pp. 373-376.
    [10] T. Yamamoto, T. Ogura, Y. Saito, K. Uwasawa, T. Tasumi, T. Mogami, “An Advanced 2.5 nm oxidized nitride gate dielectric for highly reliable 0.25μm MOSFET’s,” VLSI Tech. Symp. Dig., pp. 45-46, 1997.
    [11] L. K. Han, J. Kim, G. W. Yoon, J. Yan, and D.L. Kwong, “High Quality Oxynitride Gate Dielectrics Prepared by Reoxidation of NH3-Nitrided SiO2 in N2O Treatment,” Electron. Lett., vol. 31, p.1196-1198, 1995.
    [12] T. M. Pan, T. F. Lei, T. S. Chao, “Robust Ultrathin Oxynitride Dielectrics by NH3 Nitridation and N2O RTA Treatment,” IEEE Electron Devices Lett., vol. 2, pp. 378-380, 2000.
    [13] M. Matsui et al, “Amorphous Silicon Thin-Film Transistors Employing Photo Processed Tantalum Oxide Films as Gate Insulators,” JJAP., vol. 29, pp. 62, 1990.
    [14] J. L. Autra et al, “Fabrication and Characterization of Si-MOSFET’s with PECVD Amorphous Ta2O5 Gate Insulator,” IEEE Electron Devices Lett., vol. 18, pp.447, 1997.
    [15] S. O. Kim et al, “Fabrication of n-Metal-Oxide Semiconductor Field Effect Transistor with Ta2O5 Gate Oxide Prepared by Plasma Enhanced Metal-organic Chemical Vapor Deposition,” J. Vac. Sci. Technol. B, vol. 12, No. 5, pp. 3006, 1994.
    [16] I. Asona et al, “1.5 nm Equivalent Thickness Ta2O5 High-k Dielectric with Rugged Si Suited for Mass Production of High density DRAMs,” IEDM’98., pp. 755-758.
    [17] Yi-Lee Huang, Study of Ta2O5 as Ultra-thin Stacked Gate Material and Leakage Current Reduction by Plasma Annealing, 1997.
    [18] H. F. Luan, B. Z. Wu, L. G. Kang, B. Y. Kim, R. Vrtis, D. Robert, and D. L. Kwong, “Ultra Thin High Quality Ta2O5 Gate Dielectric Prepared by In-situ Rapid Thermal Processing,” IEDM’98, pp. 609-612.
    [19] H. F. Luan, S. J. Lee, C. H. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Roberts, and D. L. Kwong, ”High Quality Ta2O5 Gate Dielectrics with Tox,eq<10Å,” IEDM’99, pp. 141-144.
    [20] K. W. Kwon, C. S. Kang, S. O. Park, H. O. Kang, and S. T. Ahn, “Thermally Robust Ta2O5 Capacitor for the 256-Mbit DRAM,” IEEE Trans. Electron Device, vol. 43, No. 6, pp. 919-923, 1996.
    [21] S. C. Sun and T. F. Chen, “Leakage Current Reduction in Chemical- Vapor Deposition Ta2O5 Films by Rapid Thermal Annealing in N2O,” IEEE Electron Device Lett., vol. 17, No. 7, pp. 355-357, 1996.
    [22] S. C. Sun and T. F. Chen, “A New Post-Deposition Annealing Method Using Furnace N2O for Reduction of Leakage Current of CVD Ta2O5 Storage Capacitors,” IEDM’96, pp.687-690.
    [23] Yuichi Matsui, Kazuyoshi Torii, Misuzu Hirayama, Yoshihisa Fujisaki, Shimpei Iijima, and Yuzuru Ohji, “Reduction of Current Leakage in Chemical-Vapor Deposited Ta2O5 Thin-Films by Oxygen-Radical Annealing,” IEEE Electron Devices Lett., vol. 17, No. 9, pp. 431-433, 1996.
    [24] H. Shinriki and M. Nakata, “UV-O3 and Dry-O2: Two Step Anealed Chemical Vapor Deposited Ta2O5 Films for Storage Dielectric of 64-Mb DRAM’s,” IEEE Trans. Electron Devices, vol. 38, No. 3, pp. 455-462, 1991.
    [25] Feng Wensiu, Chen Pusheng, Huang Shiping, “Study on Oxygen Distribution and Oxided Mechanism for Ultrathin Oxided Si3N4 by Rapid Thermal Oxdation,” IEEE, 1996.
    [26] E. C. Carr, K. A. Ellis, and R. A. Buhrman, “N Depth Profile in Thin SiO2 Grown or Processed in N2O: The Role of Atomic Oxygen,” Appl. Phys. Lett., vol. 66, pp. 1492-1494, 1995.
    [27] W. Ting, G. Q. Lo, J. Ahn, T. Y. Chu, and D. L. Kwong, “MOS Characteristics of Ultrathin SiO2 Prepared by Oxidizing Si in N2O,” IEEE Electron Device Lett., vol. 12, pp. 416-418, 1991.
    [28] G. W. Yoon, A. B. Joshi, J. Kim, and D. L. Kwong, “MOS Characteristics of NH3-Nitrided N2O-Grown Oxides,” IEEE Electron Device Lett., vol. 14, pp. 179-181, 1993.
    [29] Y. Shi, X. Wang, and T. P. Ma, “Electrical Properties of High-Quality Ultrathin Nitride/Oxide Stack Dielectrics,” IEEE Transactions on Electron Devices, Vol. 46, No. 2, 1999.
    [30] S. M. Sze, “Current Transport and Maximum Dielectric Strength of Silicon Nitride Films,” J. Appl. Phys., 1967.
    [31] E. Suzuki and Y. Hayashi, “Carrier Conduction and Trapping in Metal-Nitride-Oxide Semiconductor Structure,” J. Appl. Phys., 1982.
    [32] D. V. Tsu, G. Lucovsky, and M. J. Mantini, “Local Atomic Structure in Thin Films of Silicon Nitride and Silicon Dioxide Produced by Remote Plasma Enhanced Chemical-Vapor Deposition,” Phys. Rev., 1986.
    [33] K. Kobayashi, A. Teramoto, and M. Hirayama, “Charge Transport in Ultrathin Silicon Nitrides,” J. Electrochem. Soc., 1995.
    [34] Bone Fung Wu, Electric Property Improvement of Sub-micro MOSFET by Two-Step Nitirded Oxide and α-Si Gate Electrode, 2000
    [35] Chao Sung Lai, Tien Sheng Chao, Tan Fu Lei, Chung Len Lee, Tiao Yuan Huang, Chun Yen Chang, “Improvement of Reliability of Metal-Oxide Semiconductor Field-Effect Transistors with N2O Nitrided Gate Oxide and N2O Polysilicon Gate Reoxidation”, JJAP, Vol. 37, p. 5507, 1998.
    [36] C. G. Parker, G. Lucovsky, J. R. Hauser, “Ultrathin Oxide-Nitride Dielectric MOSFET’s”, IEEE Electron Device Lett., Vol. 19, No. 4, p. 106, 1998.
    [37] C. Chaneliere , J. L. Autran, R. A. B. Devine, “Conduction Mechanisms in Ta2O5/SiO2 and Ta2O5/Si3N4 Stacked Structures on Si”, J. Appl. Phys., Vol. 86, July, 1999.
    [38] S. C. Song, H. F. Luan, C. H. Lee, A. Y. Mao, S. J. Lee, J. Gelpey, S. Marcus, and D. L. Kwong, “Ultra Thin High Quality Stack Nitride/Oxide Gate Dielectrics Prepared by In-situ Rapid Thermal N2O Oxidation of NH3-nitrided Si”, VLSI Tech. Symp. Dig., pp. 137-138, 1999.
    [39] W. J. Lee, H. G. Kim, and S. G. Yoon,“Microstructure Dependence of Electrical Properties of (Ba0.5Sr0.5)TiO3 Thin Film Deposited on Pt/SiO2/Si”, J.Appl. Phys. 80(10), pp. 5891-5894,15 November 1996.
    [40] S. Fang, S. Murakawa, and J. P. McVittie, IEDM, p.61, 1992.
    [41] J. P. McVittie, Plasma Process-Induced Damage, p.7, 1996.
    [42] K. Hashimoto, Jpn. J. Appl. Phys., vol. 32, p.6109, 1993.
    [43] K. Hashimoto, Jpn. J. Appl. Phys., vol. 33, p.6013, 1994.
    [44] K. P. Cheung et. al., IEDM, p.437, 1997.
    [45] K. Lai et. al., IEDM, p.319, 1995.
    [46] D. Bollinger et. al., Solid State Tech., p.111, 1984.
    [47] D. Bollinger et. al., Solid State Tech., p.167, 1984.
    [48] Shawming Ma et al,IEEE Electron Device Letters, p420, 1997.
    [49] K.P.Cheung, IEEE Electron Device Letters, p460, 1994.
    [50] P.Z.Cheung, J.C.Li, C.C.Yeh, K.S.Chang-Liao, 4th International Symp .on Plasma Process Induced Damage, p100, 1999.
    [51] H.J.Tao et al, 3th International Symp. on Plasma Process Induced Damage, p60, 1998.
    [52] K.Hashimoto et al, Appl.Phys.Lett, p1507, 1993.
    [53] Koichi Hashimoto et al, Jpn.J.Appl.Phys, p6013, 1994.
    [54] H. C. Shin et. al., Semicond. Sci. Technol., vol. 11, p.463, 1996.
    [55] K. P. Cheung et. al., J. Appl. Phys., vol. 75, p.4415, 1994.
    [56] T. Watanabe, Y. Yoshida, Solid State Tech., p.213 ,1984.
    [57] J.P. McVittie, “Process Charging in ULSI: Mechanisms, Impact and Solutions” IEDM , p.433 ,1997.
    [58] H.Shin, “Thin Gate Oxide Damage Due to Plasma Processes” Semicon. Sci. Technol.11, p.463 ,1996.
    [59] T.Watanable, Solid State Technology, 27, p263, 1984.
    [60] Y.Kawamoto, Dry Process Symposium, Oct, p132, 1985.
    [61] H.Shin, IEEE EDL, 14, p88, 1993.
    [62] H.Shin, Solid State Tech, p29, 1993.
    [63] C.T.Gabriel, J.Vac.Sci.Tech.B, 9, p370, 1991.
    [64] S. Fang et al, “Thin Oxide Damage From Gate Charging During Plasma Processing”, IEEE Electron Device Lette, Vol.13, No.5, p.288, 1992.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE