研究生: |
廖紳凱 |
---|---|
論文名稱: |
考量等候時間限制之半導體生產排程問題 The Study of Production Scheduling Problems for Semiconductor under Limited Waiting Time |
指導教授: | 阮約翰 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2004 |
畢業學年度: | 92 |
語文別: | 中文 |
論文頁數: | 71 |
中文關鍵詞: | 成批機台 、生產績效指標 、等候時間限制 、動態派工法則 |
外文關鍵詞: | Batch processing machine, Production performance indices, Limited waiting time, Dynamic dispatching rule |
相關次數: | 點閱:3 下載:0 |
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半導體晶圓廠複雜的製程流程裡,包括有等候時間限制、再迴流特性、成批機台等,以及製造現場常會發生一些不可預期事件,如機台當機、晶圓重工、良率隨機性等,都使得晶圓廠生產規劃與控制更加困難且複雜。各晶圓廠莫不致力於各種生產控制策略的考量與評估,以期降低其對系統生產績效的影響。
在以往的文獻中有許多關於成批機台的派工法則,如DBH、NACH、MCR以及DJAH。皆僅考慮單一成批機台的最佳化。但是這些方法都沒有考量等候時間限制、上、下游資訊。因此,本論文主要針對串聯之成批機台製程,在機台間具有等候時間限制的環境下,考量上、下游工件資訊,經由修改DJAH法則,提出一適合此環境的動態派工法則(R-DJAH)。並藉以達到降低生產週期時間、減少系統內在製品數量與重工次數的目標。
接著利用實驗設計的手法,以生產線交通密度作為環境因子,並以最小批量法則與本文所提出的動態派工法則之生產績效做比較。經模擬實驗分析,發現R-DJAH在各種生產績效(平均週期時間、總重工數量、系統內WIP數量)均明顯有較優異的表現,且較具穩健性(robust)。
Wafer fabrication, one of the key processes in semiconductor manufacturing, is the most complex manufacturing process. It is complicated processes to involve reentrant characteristics, queue time limit and batching requirement. It exist some uncertainties like machine down and rework and yield, etc. They make its production planning and control even harder. Each semiconductor wafer fabrication plant devotes to develop a control policy that can improve production performance indices.
In order to analyze the impact of limited waiting time and the information of upstream and downstream on product environments, In this paper, we are going to propose a new dispatching rule R-DJAH which can reduce the cycle time, the number of wafer rework and the number of the WIP in the system.
Finally, by using simulation and design of experiment, we compare the production performance indices of R-DJAH and MBS. The factor of design of experiment is production traffic density. Results indicate that the R-DJAH is significant better and robust in average cycle time, the total number of wafer rework and the number of WIP in the system.
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