簡易檢索 / 詳目顯示

研究生: 王勝弘
Wang, Sheng-Hung
論文名稱: 反覆式磁性隨機存取記憶體操作電流之搜尋方法
Toggle MRAM Operating Current Search Method
指導教授: 吳誠文
Wu, Cheng-Wen
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 63
中文關鍵詞: 反覆式磁性隨機存取記憶體操作電流可靠度使用壽命操作區間飄移
外文關鍵詞: toggle MRAM, operating current, reliability, life-time, operating region shift
相關次數: 點閱:4下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨著製程科技的演進,製造晶片時,因為製程不穩定所導致的問題也日益增加。在本篇論文中,我們將探討反覆式磁性隨機存取記憶體 ( Toggle MRAM ) 在深微米時代,因為製程變異而產生的操作區間漂移問題 ( operating region shift problem )。因為操作區間漂移,使得原先給定的操作電流無法成功得讓記憶體內的所有記憶體單元 ( memory cell ) 能夠被正常的操作。當操作區間漂移程度加大時,無法被正常操作的記憶體單元數目增加,就會造成此記憶體失效 ( Fail ),而使得整個製造過程的良率下降。我們提出了一個快速搜尋操作電流的方法,為每一個反覆式磁性隨機存取記憶體找到適合它們操作的操作電流,並提出實現此搜尋方法的內嵌式電路:電流選擇器 ( Current Selector ),以及提出電流選擇器之產生器 ( Current Selector Generator ) 為各種不同特性、規格及大小的反覆式磁性隨機存取記憶體產生對應的電流選擇器硬體架構。由模擬結果可知,與傳統的搜尋方法相比,在不同的操作區間偏移量下,本搜尋方法可節省10到30倍的搜尋操作電流時間。電流選擇器所占的面積比重也很低,對於一個16Mb的反覆式隨機存取記憶體晶片而言,電流選擇器所占的面積比重只有0.01%。透過電流選擇器的幫助,使用者就能夠使得原本因操作區間飄移而失效的記憶體,因為找到適合它們的操作電流而能夠被正常使用,進而達到製造良率的提升。另一方面,當記憶體被使用一段時間後,也可以利用電流選擇器,找到飄移過後的操作電流,以增加記憶體的可靠度 ( reliability ) 以及使用壽命 ( life-time )。


    Magnetic Random Access Memory (MRAM) is a non-volatile memory which is widely researched because of its high speed, high density, small cell size, and almost unlimited endurance. There are many types of MRAM. The toggle MRAM is the most popular one because it solves the half-select problem and has a large operating region distribution. It is operated by applying the operating current including the write word line current (IWWL) and the bit line current (IBL). For deep-submicron process technologies, the variation among the MRAM cells’ operating regions is significant. The operating region shift problem results in the write failure to cells under the operating current of specification and reduces the production yield. In tradition, we characterize the failed MRAM chips to search for the suitable operating current for them. However, the conventional characterization method is inflexible and time-consuming. In this thesis, we propose an operating current search method and design the corresponding built-in circuit, Current Selector, for toggle MRAM, which can rapidly find the customized operating current for each chip. Compared to the conventional characterization method, the proposed search method is 10 to 30 times faster while the built-in Current Selector circuit costs little area overhead (0.01% for a 16 Mb MRAM). With the built-in Current Selector, we can dynamically reconfigure the operating current of the MRAM chip for improving its reliability and increasing its life-time. Meanwhile, those chips failing to write under the operating current of specification can be identified and possibly corrected, and consequently the yield is improved.

    Abstract 1 Introduction 1.1 Motivation and Previous Works 1.2 The Proposed Approach 1.3 Thesis Organization 2 Operating Region Shift of the MRAM Device 2.1 Operation of Toggle MRAM 2.2 Operating Region Distribution 3 Operating Current Searching Methods 3.1 Spiral Search and Maximum Search 3.1.1 Spiral Search 3.1.2 Maximum Search 3.1.3 Analysis and Comparison 3.1.4 Error Estimation 3.2 Low Power Operating Current Search 4 Implementation 4.1 Requirement 4.2 Current Selector 4.2.1 In/Output Specification 4.2.2 Current Search Mode 4.2.3 Current Search Flow 4.2.4 Architecture 4.3 Current Selector Generator 4.3.1 Input Data Format 4.3.2 Data Analysis 5 Experimental Results 5.1 Simulation Environment 5.2 Current Search Time Comparison 5.3 Yield Improvement and Area Overhead 6 Conclusion and Future Work 6.1 Conclusion 6.2 Future Work

    [1] M. Durlam, Y. Chung, M. DeHerrera, B.N Engel, G. Grynkewich, B. Martino, B. Nguyen, J. Salter, P. Shah, and J.M. Slaughter, “MRAM Memory for Embedded and Stand Alone Systems”, in Proc. IEEE Int’l Conf. on IC Design & Technology (ICICDT), May 2007, pp. 1-4.
    [2] M. Durlam, B. Craigo, M. DeHerrera, B.N. Engel, G. Grynkewich, B. Huang, J.Janesky, M. Martin, B. Martino, J. Salter, J.M. Slaughter, L. Wise, and S. Tehrani, “Toggle MRAM: A highly-reliable Non-Volatile Memory”, in Proc. IEEE Int’l Symp. on VLSI Technology, Systems and Applications (VLSI-TSA), April 2007, pp. 1-2.
    [3] N. Sakimura, R. Nebashi, H. Honjo, S. Saito, Y. Kato, and T. Sugibayashi, “A 500-MHz MRAM Macro for High-performance SoCs”, in Proc. IEEE Asian Solid-State Cir. Conf. (ASSCC), Nov. 2008, pp. 3-5.
    [4] J.M. Slaughter, “Recent Advances in MRAM Technology”, in Proc. IEEE Device Research Conference (DRC), June 2007, pp. 245-245.
    [5] D.C. Worledge, P.L. Trouilloud, M.C. Gaidis, Y. Lu, D.W. Abraham, S. Assefa, S. Brown, E. Galligan, S. Kanakasabapathy, J. Nowak, E. O’Sullivan, R. Robertazzi, G. Wright, and W. J. Gallagher, “Materials and devices for reduced switching field toggle magnetic random access memory”, Jour. of Appl. Phys., , Vol. 100, Oct. 2006, pp. 074506-074506-6.
    [6] S. Tehrani, “Status and Outlook of MRAM Memory Technology (Invited)”, in Proc. IEEE Int’l Electron Devices Meeting (IEDM), Dec. 2006, pp. 1-4.
    [7] C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, “MRAM defect analysis and fault modeling”, in Proc. Int’l Test Conf. (ITC), Charlotte, Oct. 2004, pp. 124-133
    [8] C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, “Testing MRAM for write disturbance fault”, in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct. 2006.
    [9] K. Shimura, N. Ohshima, S. Miura, R. Nebashi, T. Suzuki, H. Hada, S. Tahara, H. Aikawa, T. Ueda, T. Kajiyama, and H. Yoda, “Magnetic and Writing Properties of Clad Lines Used in a Toggle MRAM”, IEEE Trans. on Magnetic, vol. 42, Oct. 2006, pp. 2736-2738.
    [10] C.-C. Hung, Y.-J. Lee, M.-J. Kao, Y.-H. Wang, R.-F. Huang, W.-C. Chen, Y.-S. Chen, K.-H. Shen, and M.-J. Tsai, “Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme”, Applied Physics Letters, vol. 88, Mar. 2006, pp. 112501-112501-3.
    [11] J. Akerman, P. Brown, M. DeHerrera, M. Durlam, E. Fuchs, D. Gajewski, M. Griswold, J. Janesky, J. Nahas and S. Tehrani, “Demonstrated reliability of 4-Mb MRAM”, IEEE Trans. on Device and Materials Reliability, vol. 4, Sept. 2004, pp. 428-435.
    [12] Y. Fukumoto and N. Kasai, “Effect of Structures of NiFe-Based Free Layers on Writing Properties in Toggle MRAMs”, IEEE Trans. on Magnetics, vol. 43, June 2007, pp. 2343-2345.
    [13] L. Savtchenko, B.N. Engel, N.D. Rizzo, M.F. Deherrera, and J. Janesky, “Method of writing to scalable magnetoresistive random access memory element”, U.S. Patent No. 6545906, Apr. 2003.
    [14] D.C. Worledge, “Spin flop switching for magnetic random access memory”, Applied Physics Letters, vol. 84, May 2004, pp. 4559-4561.
    [15] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Elsevier (Morgan Kaufmann), San Francisco, 2006.
    [16] C. Cheng, C.-T. Huang, J.-R Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST Compiler for Embedded Memories”, in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFTVS), Oct. 2000, pp. 299-307.
    [17] Agilent Technologies, “Manual of the Agilent 93000 SOC series, System Reference”, June 2004.
    [18] T.W. Andre, J.J. Nahas, C.K. Subramanian, B.J. Garni, H.S. Lin, A. Omair, and W.L. Martino, “A 4-Mb 0.18μm 1T1MTJ Toggle MRAM With Balanced Three Input Sensing Scheme and Locally Mirrored Unidirectional Write Drivers”, IEEE Jour. of Solid-State Circuits (JSSC), vol. 40, Jan. 2005, pp. 301-309.
    [19] T. Sugibayashi, N. Sakimura, T. Honda, K. Nagahara, K. Tsuji, H. Numata, S. Miura, K. Shimura, Y. Kato, S. Saito, Y. Fukumoto, H. Honjo, T. Suzuki, K. Suemitsu, T. Mukai, K. Mori, R. Nebashi, S. Fukami, N. Ohshima, H. Hada, N. Ishiwata, N. Kasai, and S. Tahara, “A 16-Mb Toggle MRAM With Burst Modes”, IEEE Jour. of Solid-State Circuits (JSSC), vol. 42, Nov. 2007, pp. 2378-2385.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE