隨著影像和多媒體技術的蓬勃發展，應用在嵌入式系統上的高效能低耗能數位訊號
處理器的地位便水漲船高。對嵌入式系統設計者而言，減少電力消耗和減低設計複
雜度是一項重要的工作。因此現在數位訊號處理器的趨勢便朝向以分散式暫存器和
叢集式架構為主的設計，以減少暫存器間的讀取和寫入通道。這種新的設計趨勢便
為編譯器最佳化技術帶來了新的挑戰。在這篇論文中，我提出了一套針對現代數位
訊號處理器設計架構而改良的資料傳遞技術，實驗證明這套技術確實能避免傳統資
料傳遞時可能造成的效能浪費。
我提出了一套考量數位訊號處理器硬體架構的資料流分析方法，此方法用來估
計資料在暫存器之間流動所需的額外花費，並找出一條最短的傳遞路徑，以避免資
料在此架構上流動而造成的效能消耗。由於估算資料流動的模型與硬體架構有密切
的關係，因此我提出三種估算模型來描述資料在此硬體架構上的流動花費：Inter
Cluster、Intra Cluster Communication Cost及Ping-Pong Register Constraint Cost。另外，
我也利用這三個模型提出了一套尋找最佳傳輸路徑的演算法，並將此演算法結合到
PAC ORC編譯器系統中以證明此方法的有效性，我的實驗平台為以PAC 2.0架構為
平台的模擬器ISS，實驗結果顯示我們的方法相對於傳統的資料傳遞技術，對浮點數
運算的DSP STONE測試程式可減少平均約13% 的效能浪費。

High-performance and low-power VLIW DSP processors are increasingly
deployed on embedded devices to process video and multimedia
applications. For reducing power and cost in designs of VLIW DSP
processors, distributed register files and multi-bank register
architectures are being adopted to reduce the amount of read/write
ports in register files. This presents new challenges for devising
compiler optimization schemes for such architectures. In our
research work, we address the compiler optimization issues for PAC
architecture, which is a 5-way issue DSP processor with distributed
register files. We show how to support an important class of
compiler optimization problems, known as copy propagations, for such
architectures. We illustrate that a naive deployment of copy
propagations in embedded VLIW DSP processors with distributed files
might result in performance anomaly. In our proposed scheme, we
derive communication cost models by cluster distance, register port
pressures, and the movement type of register sets. The cost models
are used to guide the data flow analysis for supporting copy
propagations over PAC architectures. Experimental results show that
our schemes are effective to prevent performance anomaly with copy
propagations over embedded VLIW DSP processors with distributed
files.

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