頻寬控制單元與相位抖動自我量測的數位控制適應性鎖相迴路

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研究生：	胡敏弘 Min-Hung Hu
論文名稱：	頻寬控制單元與相位抖動自我量測的數位控制適應性鎖相迴路 A Digital Control Adaptive PLL with Bandwidth Control Unit and Jitter Measurement BIST
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	171
中文關鍵詞：	適應性、鎖相迴路
外文關鍵詞：	adaptive, phase lock loop
相關次數：	點閱：3 下載：0
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　　一般的鎖相迴路，由迴路中的低通濾波器(Low-Pass Filter)控制整個迴路的頻寬，進而影響著迴路的鎖定時間(Locking Time)與穩態下的相位抖動(Jitter)。當低通濾波器的頻寬被設計的越寬，反應速度越快，就可以在系統啟動、或是頻率切換時較快達成穩態，有效縮短鎖定時間。然而低通濾波器原本的目的即是濾除高頻雜訊以及平緩壓控震盪器(Voltage-Control Oscillator)輸入電壓的快速變化，提高的頻寬將會導致雜訊的增加、壓控震盪器輸入電壓以及輸出頻率的漣波(Ripple)，進而造成輸出訊號的相位抖動。因此，一般的鎖相迴路，鎖定時間與相位抖動難以兼顧，必須由頻寬來做取捨。

　　然而，若是讓迴路依據鎖定狀態，動態調整低通濾波器的頻寬，就能維持原本相位抖動量並有效提升鎖定速度，這樣的概念即為適應性鎖相迴路(Adaptive Phase-Lock Look)。實現適應性(Adaptive)的概念有很多種方法，近幾年常用的方法大多是增加第二組相位/頻率偵測器(Phase-Frequency Detector)、低通濾波器與電荷幫浦(Charge Pump)。透過在第二組相位/頻率偵測器之中加入一些延遲單元(Delay Cell)，即可實現雙斜率(Dual-Slope)的相位/頻率偵測器。

　　然而此類作法的缺點是第二組的低通濾波器會讓晶片面積大幅增加、且在製程變異下延遲單元的延遲時間難以控制也缺乏彈性。由於電容與電阻在積體電路中所佔面積較大，卻也是濾波器必備的元件，因此第二組低通濾波器將無可避免的大幅增加晶片面積。而延遲單元的延遲時間則會因製程變異而產生誤差，這樣的誤差是設計時難以掌控的，如此結果不但可能影響經過設計的雙斜率的效能，甚至可能影響系統穩定性。此外，在這樣的設計下，延遲時間是固定而缺乏彈性的，對於不同頻率的輸入訊號，將有可能與此延遲時間無法配合而對系統穩定性造成影響。

　　在此研究專題中，提出另一種適應性概念的實現方法。透過一個量測相位差異的簡易迴路，比較輸入訊號與鎖相迴路中回授訊號的相位差異，準確的判斷相位差異量，輸出數位訊號以頻寬控制單元 BCU (Bandwidth Control Unit) 來控制低通濾波器的頻寬與電流幫浦的電流量。如此將不再有第二組低通濾波器的需求，避免了晶片面積的大幅增加。而這樣的作法不僅可以產生穩定且不受製程影響的控制訊號，實現適應性鎖相迴路的概念；甚至可以 off-chip 的方式實現頻寬控制單元 BCU，進而做到 programmable，對頻寬達到較佳的控制；同時可將此數位訊號輸出，得到測量相位差異的自我測試電路(Built-in Self-Test)。

In this thesis, a digital control adaptive PLL with a BCU (Bandwidth Control Unit) and jitter measurement BIST is proposed to reduce the locking time as well as measure the long-term jitter of the PLL. The locking status is detected and digitized by the measurement BIST, which sends signal to the BCU and controls the loop bandwidth. Thus the loop bandwidth could automatically switch to two times of the normal bandwidth when it's out of lock and the locking time could be reduced 50% ideally according to the mathematic model.

The normal loop bandwidth is 3MHz in steady state and the wider loop bandwidth is 6MHz when out of lock. The PLL is implemented under TSMC 0.18μm CMOS process and the supply voltage is 1.8V. The input frequency is 50MHz and the output frequency is 1.6GHz. The post-simulation result shows that the locking time is 0.89μs in the proposed digital control adaptive PLL and 1.37μs in conventional PLL with 3MHz fixed loop bandwidth.

中文摘要
Abstract
List of Contents
List of Figures
List of Tables.
Chapter 1.  Introduction
       1.1 Motivation.
       1.2 Technique Review.
       1.3 Thesis Outline
Chapter 2.  PLL and Adaptive Function
      2.1 PLL Overview
         2.1.1 PFD (Phase-Frequency Detector)
         2.1.2 CP (Charge Pump)
         2.1.3 LF (Loop Filter)
         2.1.4 VCO (Voltage-Control Oscillator)
         2.1.5 FD (Frequency Divider)
      2.2 PLL Analysis
         2.2.1 Frequency-Domain Open-Loop Analysis
         2.2.2 Frequency-Domain Close-Loop Analysis
         2.2.3 Time-Domain Close-Loop Analysis
      2.3 Trade-off in Bandwidth and Adaptive Function
      2.4 PLL System Design
Chapter 3.  Proposed Jitter Measurement
      3.1 Jitter Measurement Overview
         3.1.1 The Jitter
         3.1.2 Technique Review
      3.2 Previous Jitter Measurement Algorithm
         3.2.1 Long-Term Jitter and Output Jitter
         3.2.2 Previous Jitter Measurement Algorithm
         3.2.3 Robust Issue Analysis
      3.3 Modified Jitter Measurement Algorithm
         3.3.1 Capacitor Accuracy
         3.3.2 Threshold Voltage and Vbase
         3.3.3 Comparator with Hysteresis
      3.4 Proposed Charge Pump
         3.4.1 Resolution and Current Accuracy
         3.4.2 Previous Charge Pump
         3.4.3 Proposed Charge Pump
      3.5 Simulation Result and Conclusion
         3.5.1 Simulation Result in Previous Work
         3.5.2 Simulation Result in This Work
         3.5.3 Conclusion
Chapter 4.  Proposed Adaptive PLL
      4.1 Adaptive PLL Algorithm
         4.1.1 Bandwidth Switching Algorithm
         4.1.2 Bandwidth Controlling Algorithm
      4.2 Proposed Circuits.
         4.2.1 BCU (Bandwidth Control Unit)
         4.2.2 Adaptive Loop Filter with shrunk Capacitor
         4.2.2 Adaptive Charge Pump
      4.3 Whole Adaptive Phase-Lock Loop
Chapter 5.  Simulation Result and Layout
      5.1 Simulation Result
      5.2 Layout and Post-Simulation
      5.3 Specification
Chapter 6.  Comparison and Conclusion
      6.1 Comparison
         6.1.1 Comparison of Algorithm
         6.1.2 Comparison of Simulation Result
      6.2 Conclusion
      6.3 Future Work
Bibliography

                                

[1] R. E. Best, Phase-Locked Loops Design, Simulation, and Applications, 3rd ed. New York: McGraw-Hill, 1997.
[2] D. Rosemarine, “Accurately calculate PLL charge pump filter parameters,” Microwaves RF, pp. 89-94, Feb. 1999.
[3] O. T. C. Chen, R. R. B. Sheen, “A power-efficient wide-range phase locked loop,” IEEE J. Solid State Circuits, vol. 37, pp. 51-62, Jan. 2002.
[4] J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, “A wide-band width low-voltage PLL for PowerPC™ microprocessors,” IEEE J. Solid State Circuits, vol. 30, pp. 383-391, Apr. 1995.
[5] J. Hakkinen, J. Kostamovaara, “Speeding up an integer-N PLL by controlling the loop filter charge,” IEEE Transactions, Analog and Digital Signal Processing, Circuits and Systems, Vol. 50, Iss. 7, pp. 343-354, July 2003.
[6] L. Liu, B. Li, “Reduced pull-in time of phase-locked loops with a novel nonlinear phase-frequency detector,” Proc. of Microwave Conference, Proc. of Asia-Pacific Conf. Vol. 5, Dec. 2005.
[7] Y. F. Kuo, R. M. Weng, Chuan-Yu Liu, “A Fast Locking PLL With Phase Error Detector,” Conf. of Electron Devices and Solid-State Circuits, Dec. 2005 pp. 423-426.
[8] C. Y. Yang; S. I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” Journal of Solid-State Circuits, Vol. 35, Iss. 10, pp. 1445-1452, Oct. 2000..
[9] K. H. Cheng, W. B. Yang, Cheng-Ming Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” IEEE Transactions, Analog and Digital Signal Processing, Circuits and Systems, Vol. 50, Iss. 11, pp. 892-896, Nov. 2003.
[10] Y. S. Choi, H. H. Choi, T. H. Kwon, “An adaptive bandwidth phase locked loop with locking status indicator,” Proc. KORUS, Science and Technology, pp. 826-829, 2005.
[11] T. Xia, J.C. Lo, “Time-to-voltage converter for on-chip jitter measurement,” IEEE Transactions on Instrumentation and Measurement, pp. 1738-1748, Vol. 52, Iss. 6, Dec. 2003.
[12] J.G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, Iss. 11, pp. 1723-1732, Nov. 1996.
[13] E. J. Hernandez, A. Diaz Sanchez, “Positive feedback CMOS charge-pump circuits for PLL applications,” Proc. of the 44th IEEE 2001 Midwest Symposium, MWSCAS, Circuits and Systems, Vol. 2, pp. 836-839, Aug. 2001.
[14] L. Joonsuk, K. Beomsup, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE Journal of Solid-State Circuits, Vol. 35, Iss. 8, pp. 1137-1145, Aug. 2000.
[15] T. Yamaguchi, M. Soma, D. Halter, R. Raina, J. Nissen, and M. Ishida, “A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals,” in Proc. IEEE VLSI Test Symp., pp. 102-110, 2001.
[16] T.Yamaguchi, M. Soma, M. Ishida, T. Watanabe ,and T. Ohmi, “Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method,” Proc. IEEE VLSI Test Symp., 2000.
[17] S. Cherubal and A. Chatterjee, “A high-resolution jitter measurement techniques using ADC sampling,” in Proc. Int. Test Conf., pp. 838-847, 2001.
[18] L. Angrisani, A. Baccigalupi, and L. Ferrigno, “Jitter measurement from theory to practice,” in Proc. Instrumentation and Measurement Conf., vol. 3, pp. 1435-1439, 2000.
[19] A Novel Jitter Measurement Method with Built-In Oscillation Test Structure for Phase Locked Loops
[20] A. Stevens, R. Van Berg, J. Van der Splegel, and H. Williams, “A time-to voltage converter and analog memory for colliding beam detectors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1748-1752, Dec. 1989.
[21] M. Tanaka, H. Ikeda, M. Ikeda, and S. Inaba, “Development of a monolithic time-to-amplitude converter for high precision TOF measurement,” IEEE Trans. Nucl. Sci., vol. 38, pp. 301-305, Apr. 1991.
[22] A. H. Chan, G. -W. Roberts, “A jitter characterization system using a component-invariant Vernier delay line,” IEEE Trans. of Very Large Scale Integration (VLSI) Systems, Vol. 12, Iss. 1, pp. 79-95, Jan. 2004.
[23] M. S. Gorabies, J. Kelly, K. -M. Roberts and R. -L.Sumner, “A high resolution multihit time to digital converter integrated circuit,” IEEE Trans. Nuclear Sci., vol. 44, pp. 379-384, Mar. 1997.
[24] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997.
[25] R.J. Baker, H.W. Li, D.E. Boyce, CMOS circuit design, layout, and simulation , New York, IEEE Press, 1998.
[26] Philip E. Allen and Douglas R Holberg, CMOS Analog Circuit Design (Oxford University Press, Inc, USA, 2002), 2nd edition, pp. 259-397

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