在高壓功率元件的開發中，如何獲得良好的崩潰電壓及導通電阻(的權衡一直是研究的重點。儘管許多的研究發表，都顯示能夠在降低導通電阻的同時，維持耐壓等級。但是，在特定的額定崩潰電壓之下阻值降低的程度終究有極限存在，而這便是我們所熟知的矽極限(Silicon-limit)。
近年來，隨著超級接面(Super Junction) 概念的提出，具有高摻雜濃度的超級接面結構能夠有效改善崩潰電壓與導通電阻之間的關係，並且可以突矽極限，因此，許多結合超級接面結構的新型高壓功率元件便應運而生。然而，在製程方面，如何使得超級接面結構中，不同摻雜類型的柱狀區載子濃度互相匹配，達到電荷平衡，更是另外一項重要的挑戰。
此論文中，我們提出一個具增進電荷平衡結構之新型600伏等級
超級接面金氧半場效電晶體(Charge-Balance-Enhanced Super Junction MOSFET，簡稱CBE-SJ MOS)，希望藉由減緩元件在製作過程中，熱步驟對載子濃度以及特性的影響，進而獲得元件最佳化的表現。並藉由TCAD軟體的模擬，使用TSUPREME4與MEDICI的搭配，達到額定電壓為600伏特並具有超低導通電阻的新型超級接面金氧半場效電晶體(CBE-SJ MOS)其晶胞與周邊耐壓結構的設計。

In designing power devices using conventional P/N junctions, the tradeoff between breakdown voltage (Bv) and on-state resistance (Ron) has always been a major concern. Many studies have proposed various structures to sustain high Bv level while reducing the Ron. However, it is generally believed that under the same Bv, there is a limit on how low Ron can be, which is called “Silicon-limit”.
By adapting the Super Junction (SJ) concept, highly doped SJ structure can effectively improve the Bv while reducing the Ron; hence break the Silicon-limit. Due to its superior characteristics, SJ has become the promising solution in high voltage power device applications. The fabrication of SJ devices faces the challenge of creating P/N pillars with matching impurity concentrations after thermal process.
This thesis introduced a novel Charge-Balance-Enhanced Super Junction MOSFET, CBE-SJ MOS; which helps to promote charge-balance in the super junctions. By TCAD simulation, the newly designed cell and termination structures of CBE-SJ MOS is proven to endure 600Volt reverse voltage with ultra low on-state resistance.

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