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研究生: 林詠嘉
Yung-Chia Lin
論文名稱: 雙繞線層球閘陣列封裝之全域繞線器
A 2-Layer Global Router for Ball Grid Array Packages
指導教授: 王廷基
Ting-Chi Wang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 32
中文關鍵詞: 球閘陣列封裝全域繞線器
外文關鍵詞: Ball Grid Array, Package, Global Router
相關次數: 點閱:3下載:0
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  • 隨著製程的進步,現今在一個超大型積體電路的設計裡,輸入輸出腳位的數目很輕易的到達幾百個,甚至數千個以上。為了因應這些大數目的輸入輸出腳位到印刷電路板的連接,現今大多採用球閘陣列封裝。在這份論文中,我們提出一個考慮減少總繞線長度及繞線溢位的雙繞線層球閘陣列封裝之全域繞線器。我們的演算法根據腳位的順序,一次做一條線的繞線。首先我們的演算法會先建立一個繞線圖,以及指定一個初始為零,代表允許最大繞線溢位的參數。接著我們的演算法會根據平面繞線的觀點中,從繞線圖裡,為每一條線抽取出一個繞線子圖。我們接著在每一條線的繞線子圖上,為每一條線做繞線。如果我們的演算法找不到一條從腳位到印刷電路板上的焊錫球的繞線路徑時,我們的演算法會擴張繞線子圖,然後重新繞線一次直到我們找到一條繞線路徑,或者是擴張的次數到達一個使用者指定的上限。為了讓我們的演算法避免讓繞線路徑穿過已經繞線溢位的區域時,我們採用歷史代價。一旦發現我們的演算法無法完成繞線時,我們會允許最大繞線溢位加一,接著重新整個繞線的過程。實驗結果指出,與一個最新的成果比較,平均而言,我們的演算法可以減少96.8%的總繞線溢位及83.33%的最大繞線溢位。除此之外,我們的演算法會產生較小的總繞線長度,並且執行時間快了4.39倍。


    As the manufacturing technology keeps shrinking, the number of I/O pins in a current VLSI design has easily grown to hundreds, or even thousands. With the pressing need of connecting the huge number of I/O pins to a PCB (Printed Circuit Board), a BGA (Ball Grid Array) package is used mostly nowadays. In this thesis, we propose a two-layer BGA global routing algorithm which routes the net in the order of fingers one at a time while considering the minimization of the total wirelength and overflow. Our algorithm begins with constructing a routing graph and assigning a parameter which represents the maximum overflow tolerance initialized to 0. Our algorithm then extracts a routing subgraph from the routing graph for each net based on the viewpoint of planar routing. Our algorithm next routes nets one at a time on their respective routing subgraphs. If our algorithm cannot find a routing path from a finger to a ball on the given routing subgraph, our algorithm will expand the routing subgraph and try to route again until our algorithm find a routing path or the number of expanding times reaches the user-specified upper bound. A history cost is introduced to make our routing algorithm avoid constructing routing paths through grids which are overflowed during previous iteration. Once it is found that our algorithm cannot finish routing a net, our algorithm will increase the maximum overflow tolerance by one and restart the whole routing process. The experimental results show that our algorithm averagely decreases 96.8% total overflow and 83.33% maximum overflow as compared to a most recent work. Besides, our algorithm produces smaller total wirelength and runs 4.39 times faster.

    Abstract (in Chinese) Abstract Contents List of Figures List of Tables Chapter 1 Introduction Chapter 2 Preliminaries Chapter 3 The Routing Algorithm Chapter 4 Experimental Results Conclusion References

    [1] H. Bakoglu, Circuits, Interconnections and Packaging in VLSI, Addison-Wesley, Reading, MA, 1990.
    [2] S.-S. Chen, J.-J. Chen, C.-C. Tsai, and S.-J. Chen, “An Even Wiring Approach to the Ball Grid Array Package Routing,” Proceedings of International Conference on Computer Design, pp.303–306, 1999.
    [3] S.-S. Chen, J.-J. Chen, S.-J. Chen, and C.-C. Tsai, “An Automatic Router for the Pin Grid Array Package,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 133–136, 1999.
    [4] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, MIT Press, pp. 350-356, 2001.
    [5] J.-W. Fang, I.-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, “A Routing Algorithm for Flip-Chip Design,” Proceedings of International Conference On Computer-Aided Design, pp. 753–758, 2005.
    [6] HITACHI Cable TAB Tape, Avaiable : http://www.hitachi-cable.co.jp/catalog/EB-104.pdf
    [7] Y. Kubo and A. Takahashi, “Global Routing by Iterative Improvements for 2-Layer Ball Grid Array Packages,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 725–733, 2006.
    [8] L. McMurchie and C. Ebeling, “Pathfinder: A Negotiation-Based Performance-Driven Router for FPGAs,” Proceedings of ACM International Symposium on FPGAs, pp. 111–117, 1995.
    [9] Y. Tomioka and A. Takahashi, “Monotonic Parallel and Orthogonal Routing for Single-Layer Ball Grid Array Packages,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 642–647, 2006.
    [10] C.-C. Tsai, C.-M. Wang, and S.-J Chen, “NEWS: A Net-Even-Wiring System for the Routing on a Multilayer PGA Package,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.17, No. 2, pp.182–189, 1998.
    [11] D. Wang, P. Zhang, C.-K. Chang, and A. Sen, “A Performance-Driven I/O Pin Routing Algorithm,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 129–132, 1999.
    [12] M.-F. Yu, J. Darnauer and W.-M. Dai, “Interchangeable Pin Rouing with Application to Package Layout,” Proceedings of International Conference On Computer-Aided Design, pp. 668–673, 1996.

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