In recent years, the design of VLSI has reached System-On-Chip (SoC) era. Re-ducing the power consumption of the circuit has thus become an important issue. Several low-power design techniques have been developed. Many low-power designs implements the equation in their design. Power consumption includes glitch power and leakage power. Since the glitch power has a greater influence on the total power consumption, we attempt to reduce it to achieve the goal of reducing cir-cuit power consumption. The solution we propose to achieve this goal is to switch synchronous input signal to asynchronous input signal techniques.

Asynchronous input signals, used in circuit design, can effectively reduce the generation of glitch power so as to reduce the power consumption of the circuit. Also, such techniques have the advantage of not keeping the structure of the original circuit, small overhead hardware, and requiring only the completion of buffer circuit. In addi-tion, the general use of this method in various circuits suggests its feasibility. By doing comparison and analysis, it will be decided if switching from synchronous input signal to asynchronous input signal actually reduces power consumption. Finally, by integrating and automating steps of this method, the designing time can be reduced.

近年來VLSI設計正邁向SoC的世代，使得降低電路中的功率消耗變成很迫切去達成的目標，因此有許許多多低功率的設計技術不斷被發展出來。低功率的設計主要根據 這個方程式，從降低方程式中的參數以實現降低功率消耗的目的。電路中功率的消耗還存在了突波功率和漏電功率兩方面之消耗，其中又以突波的功率消耗影響是較為顯著。然而本論文將朝向降低突波功率的消耗去設計，以達成降低功率的設計，為了完成此設計我們提出一套設計流程，將原本同步輸入訊號轉變為非同步輸入訊號的技巧。

當在電路設計中如果使用此非同步輸入的技巧後，可以有效去減少突波的產生來達成降低功率消耗之設計，此外不用去改變原始電路之結構，而且所需的額外硬體電路非常少，只需要簡單的緩衝器電路即可完成。另外，我們也將此技巧應用於更多的電路中，以確保此技巧的可行性。然後再去做比較與分析探討，如果我們將同步輸入訊號轉變為非同步輸入訊號後，可以降低電路中多少的功率消耗。最後把這一套技巧中的每個步驟去做整合與自動化，可以使我們節省掉許多設計上所要花費的時間。

[1] H. S. Won, K. S. Kim, K. O. Jeong, K. T. Park, K. M. Choi, and J. T. Kong, "An MTCMOS design methodology and its application to mobile computing," Pro-ceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 110- 115, 25-27 Aug. 2003.

[2] A. Raghunathan, S. Dey, and N. K. Jha, "Glitch Analysis and Reduction in Reg-ister Transfer Level Power Optimization," Design Automation Conference Pro-ceedings, pp.331-336, 3-7 Jun, 1996.

[3] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, "Digital Integrated Circuits: A Design Perspective," 2nd Edition, Prentice Hall, 2003.

[4] N. Weste, and D. Harris, "CMOS VLSI Design: A Circuit and System Perspec-tive," 3rd Edition, Addison Wesley, 2004.

[5] S. G. Narendra, "LEAKAGE IN NANOMETER CMOS TECHNOLOGIES," Springer, 2006.

[6] M. Anis, "Sub-threshold leakage current: challenges and solutions," Proceedings of the 15th International Conference on Microelectronics 2003, pp.77-80, 9-11 Dec. 2003.

[7] C. Piquet, "Low-Power CMOS circuits Technology, Logic Design and CAD Tools," CRC press, 2006.

[8] P. P. Gelsinger, "Gigascale integration for teraops performance-challenges, op-portunities, and new frontiers," Proceedings 41st Design Automation Conference, 2004, pp. xxv- xxv, 2004.

[9] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, "Low Power Metho-dology Manual: For System-on-Chip Design," Springer, 2007.

[10] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1V high-speed digi-tal circuit technology with 0.5μm multi-threshold CMOS," Proceedings Sixth Annual IEEE International ASIC Conference and Exhibit 1993, pp.186-189, 27 Sep-1 Oct 1993.

[11] F. Fallah, and M. Pedram, "Standby and Active Leakage Current Control and Mi-nimization in CMOS VLSI Circuits," IEICE Trans. on Electronics, Special Sec-tion on Low-Power LSI and Low-Power IP, vol. E88-C, no.4, pp. 509-519, Apr. 2005.

[12] W. Wolf, "Modern VLSI Design: System on Chip Design," 3rd Edition, Prentice Hall, 2002.

[13] A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Royi, and V. De, "Tech-nology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's," Proceedings 1999 International Symposium on Low Power Electronics and Design, pp. 252- 254, 1999.

[14] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current me-chanisms and leakage reduction techniques in deep-submicrometer CMOS cir-cuits," Proceedings of the IEEE, vol.91, no.2, pp. 305- 327, Feb 2003.

[15] J. M. Rabaey, and M. Pedram, "LOW POWER DESIGN METHODOLOGIES," Kluwer Academic Publishers, 1996.

[16] A. Stoica, and S. Katkoori, "“Glitch Logic” and Applications to Computing and Information Security," BLISS '09. Symposium on Bio-inspired Learning and In-telligent Systems for Security, pp.107-112, 20-21 Aug. 2009.

[17] J. P. Uyemura, "CMOS LOGIC CIRCUIT DESIGN," Kluwer Academic Publish-ers 1999.

[18] A. S. Sedra, and K. C. Smith, "Microelectronic CIRCUITS," 5th Edition, Oxford University Press, 2004.

[19] D. A. Neamen, "Electronic circuit analysis and design," 2nd Edition, McGraw-Hill, 2001.

[20] M. D. Ercegovac, and T. Lang, "Digital Arithmetic," Morgan Kaufmann Publish-ers 2004.

[21] Parhami, and Behrooz, "Computer arithmetic: algorithms and hardware designs," Oxford University Press, 2000.

[22] Texas University of ITC'99 Benchmark Circuit
URL: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html

[23] AStar-Hspice Manual, Release 2001.4, December 2001, Avant! Corporation and Avant! Subsidiary.

[24] D. G. Luenberger, "Linear and Nonlinear Programming," 3rd Edition, Addi-son-Wesley, 2008.

[25] B. K. Jeong, and W. K. Dong, "Low-Power Carry Look-Ahead Adder with Mul-ti-Threshold Voltage CMOS Technology," CAS 2007. International Semiconduc-tor Conference, 2007, pp.537-540, Oct. 15 2007-Sept. 17 2007.

[26] E. Horowitz, S. Sahni, and S. Anderson-Freed, "Fundamentals of data structures in C," Computer Science Press 1993.

[27] Shao-Min Li, Private Communications on Adder Completion Signal Generation.