電子系統層級語言平台的設立的目的是為協助當寄存器傳送語言層級平台遇到的瓶頸，如具有複雜的設計的輸入輸出，過長時間的驗證流程，尤其是遭遇到大的多核心平台寄存器傳送語言平台的模擬時間長度讓人無法忍受。然而電子系統層級語言在模擬的時間精準度會限制提升軟體的抽象層級，這篇論文呈現了是有辦法產生一個具有寄存器傳送語言層級的時間準確度的電子系統層級語言多核心模擬平台。
首先我們利用了運行在電子系統層級語言多核心平台上具有平行處理的三維繪圖兼具有光柵化軟體，因電子系統層級語言平台是依賴指令數為時間準度基準的，因此我們透過觀察這隻軟體的指令數分佈，把部分的具有高指令數的軟體透過高階模擬和合成的流程加以實作出RTL層級的硬體加速器，再利用寄存器傳送語言多核心平台驗證高階模擬和合成產生的硬體，我們嘗試把電子系統層級語言平台上所有的元件得到正確的時間延遲(可以在軟體模擬中和寄存器傳送語言層級壓縮到5%以內的誤差)。
最後，我們終於能跑透過電子系統層級語言多核心平台跑出高速的模擬，且此模擬平台兼具RTL層級的模擬時間精準度，透過電子系統層級語言相較寄存器傳送語言所具有的高度彈性，我們能利用這個ESL平台進行數據量更大且更複雜的晶片網路(10X10的網孔結構的晶片網路且具有硬體加速器的模擬)來呈現不同的硬體組態在電子系統層級語言平台上。

ESL platforms have been built to overcome the design challenges posed by RTL
including complex design entries and long verification process, especially for
large many-core architectures. However, accuracy of ESL simulation may limit
the application of raising to a higher abstraction level. In this thesis, we
demonstrate that it's possible to create a fast and accurate ESL platform.
First, we start from a parallel software for 3D graphics rasterization on a
44-mesh architecture (with an RTL definition). By profiling the software on an
ESL platform based on instruction-level accuracy (hence no timing), we
partition the part with a high-instruction count and implement it with a
high-level synthesis flow. After verifying the HLS hardware on RTL, we try to
augment the ESL platform for all components with correct timings (end-to-end
software cycle errors are less than 5\% as compared with RTL). Finally, we are
able to run a fast simulation (up to 10x10 mesh with hardware accelerators) to
show the overall performance for different configuration of hardware on the ESL
platform.

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