簡易檢索 / 詳目顯示
| 研究生： |
趙駿騰 Chao, Chun-Teng |
|---|---|
| 論文名稱： |
速度適應之可重構容錯多核心系統 Speed Adaptive Reconfigurable Fault-tolerant Multi-Core System |
| 指導教授： |
黃錫瑜
Huang, Shi-Yu |
| 口試委員: |
李進福
Li, Jin-Fu 呂學坤 Lu, Shyue-Kung 王廷基 Wang, Ting-Chi |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2024 |
| 畢業學年度： | 113 |
| 語文別： | 中文 |
| 論文頁數： | 46 |
| 中文關鍵詞： | 容錯 、多核心系統 、速度適應 |
| 外文關鍵詞： | fault-tolerant, multi-core system, speed adaptive |
| 相關次數： | 點閱：56 下載：0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著越來越多的晶片應用於汽車、航空、航天和生物醫學電子領域，“高可靠性”和“長壽命”成為兩個密切相關的需求。高可靠性確保系統的功能不易失效。長壽命意味著系統具有抵抗電路老化的能力，從而達到更長的使用壽命。
在本篇論文中，系統可以重新配置為單模（Single Mode）、雙模冗餘（DMR Mode）和三模冗餘（TMR Mode）。系統將根據不同的可靠性需求在這些模式之間切換。我們提出安全邊際機制以保護主核心的數據傳輸並抵禦無聲數據損壞（SDC）的發生。為了支持各模式的不同最大運行速度，我們集成了一個ADPLL作為系統的時鐘生成器，以動態改變時鐘速率。我們使用了90nm TSRI CMOS製程來實現這個系統。與基本的多核系統相比，這種機制增加了14.67%的面積開銷。
For more and more chips used in automotive, avionics, aerospace, and biomedical electronics, “high reliability” and “long lifetime” are two closely related demands. High reliability ensures that the functionality of the system does not fail easily. Long lifetime means that the system has the ability to resist circuit aging and thus achieves a longer lifetime.
In this work, the system can be reconfigured to work in Single Mode, DMR Mode, and TMR Mode. The system will switch among these modes according to different level of reliability. We propose a Safety Margin Mechanism to protect the data transmission of the main core and resist the occurrence of SDCs (Silent Data Corruptions). To support different maximum operating speeds of modes, we integrate an ADPLL as the system's clock generator to change the clock rate dynamically. We utilize a 90nm TSRI CMOS process for this system. Compared with the baseline multi-core system, the mechanism increases area overhead by 14.67%.
[1] G. Papadimitriou and D. Gizopoulos, "Silent Data Corruptions: Microarchitectural Perspectives," IEEE Transactions on Computers, vol. 72, no. 11, pp. 3072-3085, Nov. 2023.
[2] S. Shukla and K. C. Ray, "A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications," IEEE Access, vol. 10, pp. 44136-44146, Apr. 2022.
[3] M. Rogenmoser, N. Wistoff, P. Vogel, F. Gürkaynak and L. Benini, "On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster," Proc. of Computer Society Annual Symposium on VLSI (ISVLSI), pp. 398-401, July. 2022.
[4] M. Barbirotta, A. Cheikh, A. Mastrandrea, F. Menichelli, F. Vigli and M. Olivieri, "A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design," Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1-4, Oct. 2021.
[5] J. Mach, L. Kohútka and P. Čičák, "A New RISC-V CPU for Safety-Critical Systems," Proc. of Mediterranean Conference on Embedded Computing (MECO), pp. 1-4, June. 2023.
[6] M. Witterauf, A. Tanase, J. Teich, V. Lari, A. Zwinkau and G. Snelting, "Adaptive fault tolerance through invasive computing," Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Montreal, pp. 1-8, June. 2015.
[7] W. Yang, Y. Zhou, H. Liu and H. Dai, "Research and Implementation of Multi-Core Stack Processor Based on AXI Bus," Proc. of International Conference on Big Data, Artificial Intelligence and Internet of Things Engineering (ICBAIE), pp. 268-272, Oct. 2023.
[8] E. Strollo and A. Trifiletti, "A fault-tolerant real-time microcontroller with multiprocessor architecture," Proc. of International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 431-436, June. 2016.
[9] Ben Marshall, Dan Page, Thinh Pham, Max Whale, HYDRA: multi-core RISC-V with cryptographically interesting modes of operation, Sixth Workshop on Computer Architecture Research with RISC-V (CARRV), vol. 1, no. 1, pp. 1-6, May. 2022.
[10] F. Mireshghallah, M. Bakhshalipour, M. Sadrosadati and H. Sarbazi-Azad, "Energy-Efficient Permanent Fault Tolerance in Hard Real-Time Systems," IEEE Transactions on Computers, vol. 68, no. 10, pp. 1539-1545, Oct. 2019.
[11] M. Ebrahimi, S. G. Miremadi, H. Asadi and M. Fazeli, "Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 8, pp. 1454-1468, Aug. 2013.
[12] J. Li and Y. Wang, "Transient Fault Tolerance on Multicore Processor in AMP mode," Proc. of International Conference on Dependable Systems and Their Applications (DSA), pp. 332-337, Aug. 2021.
[13] H. -M. Pham, S. Pillement and S. J. Piestrak, "Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor," IEEE Transactions on Computers, vol. 62, no. 6, pp. 1179-1192, June 2013.
[14] Y. G. Kim, M. Kim and S. W. Chung, "Enhancing Energy Efficiency of Multimedia Applications in Heterogeneous Mobile Multi-Core Processors," IEEE Transactions on Computers, vol. 66, no. 11, pp. 1878-1889, Nov. 2017.
[15] F. Kempf and J. Becker, "Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems," Proc. of Mediterranean Conference on Embedded Computing (MECO), pp. 1-5, June. 2023.
[16] C. -E. Lee and S. -Y. Huang, "A Cell-Based Fractional-N Phase-Locked Loop Compiler," Proc. of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 273-276, July. 2018.
[17] Source CPU: https://github.com/scarv/scarv-cpu
[18] Source AXI-lite crossbar: https://github.com/alexforencich/verilog-axi