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研究生: 林家駿
Lin, Chia-Chun
論文名稱: 基於金屬-高介電氧化物-金屬結構之先進電子元件開發及應用
Advanced Electronic Devices Development and Applications Based on Metal-Insulator-Metal Structure
指導教授: 巫勇賢
Wu, Yung-Hsien
口試委員: 荊鳳德
Albert Chin
張廖貴術
K.S. Chang-Liao
李耀仁
Yao-Jen Lee
鄭淳護
Chun-Hu Cheng
學位類別: 博士
Doctor
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2014
畢業學年度: 103
語文別: 英文
論文頁數: 103
中文關鍵詞: 電容電阻式記憶體金半金結晶氧化鈦鋯
外文關鍵詞: ZrTiO
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  • 本篇論文主軸為金屬-氧化物-金屬結構的先進元件,第一種為金屬-氧化物-金屬(MIM)電容,第二種則為電阻式記憶體。
    在金氧金電容的部分,主要著重於降低電容元件的”二次電壓電容係數”,而二次電壓電容係數會隨著氧化物的介電常數增加而增高,因此目標在於如何能在提高電容密度的同時必須抑制元件的電容對施加電壓的非線性特性,在此使用的是非晶態的TiO2和Y2O3堆疊,由於Y元素在高溫下能夠有效地抑制TiO2的結晶,因此可以擁有高溫退火帶來的介電常數提高的好處但同時能抑制TiO2形成結晶態帶來過大的二次電壓電容係數,也就是藉著部份的電容密度來達到減少二次電壓電容係數。
    由於電容密度與二次電壓電容係數呈現一個反比的關係,因此需要應用另一種金氧金電容當中不同氧化物的特性,稱作二次電壓電容係數的”抵消效應”。所謂的抵消效應是藉著堆疊兩種不同的氧化物,兩種氧化物各自擁有一正一負的二次電壓電容係數,因此堆疊起來之後整體的二次電壓電容係數會被正負抵消而呈現較低的二次電壓電容係數。同時為了想進一步地提高電容密度,於此使用了結晶態的TiO2,但同時會急遽地增加二次電壓電容係數,因此除了採用抵消效應之外,還多在結晶的TiO2表面使用了氮氣電漿處理來抑制二次電壓電容係數,並且堆疊擁有負的二次電壓電容係數的SiO2,在這部分我們使得二次電壓電容係數有效的抑制達30 ppm/V2,電容密度則為11.2 fF/μm2符合國際半導體藍圖組織2018年所必須達成的要求。但與一般的金屬氧化物SiO2的介電常數低了許多,因此再進一步地將SiO2更換為ZrTiOx,ZrTiOx與SiO2一樣有著負的二次電壓電容係數,但其介電常數則高達22.5,因此能夠藉著抵消效應達到理想的二次電壓電容係數外更能提高電容密度達14.38 fF/μm2和68 ppm/V2的二次電壓電容係數。
    而在電阻式記憶體的主題中,主要在探討其中的金屬氧化物薄膜性質對整個電阻式記憶體的電性影響,在此以ZrTiOx為主角,討論ZrTiOx結晶與否對切換機制的影響;第二步則是討論非晶態ZrTiOx中若有介面氧化層(interfacial layer, IL)產生及IL位置對於電阻式記憶體的影響,分為無IL、下電極處有IL生成和上下電極都有IL存在對元件影響的比較與討論,在這一系列的實驗中得到非晶態的ZrTiOx展現了較好的均勻度、較低的切換電壓、較快的切換速度跟較好的判讀區間等等;而IL的位置在電阻式記憶體中影響著切換電壓大小的重要因素,因此IL可以是一個作為調變的因子來達到較快的速度和較低的功耗,在研究結果發現單側生成IL會有最佳的效果。除此之外,電阻式記憶體在高密度堆疊的應用上通常需要藉著額外的二極體達到整流效果和減少元件彼此間干擾導致的誤讀可能性,因此一個二極體加上一個電阻式記憶體的結構(1D1R),才有可能達到最密堆積。在此研究中使用了一個電阻式記憶體及一個金屬-半導體接面而形成的蕭基二極體,為TaN/ZrTiOx/Ni/n+-Si結構,除了搭配前述IL研究的結果外,此結構的電阻式記憶體更容易的與現今製程技術匹配外,也能降低元件的製作成本。


    This thesis focuses on the advanced devices based on the metal-insulator-metal (MIM) structure, the first one is MIM capacitor, and another one is resistive random access memory (RRAM).
    The first part is MIM capacitor, our works revolve around how to suppress the quadratic voltage coefficient of capacitance, so called, VCC-α. However, VCC-α will become larger as the dielectric constant of oxide increases that brings out our main goal, how to increase the capacitance density but suppress VCC-α at the same time. In this part, we adopted amorphous TiO2 and Y2O3 stack as dielectric of MIM capacitor, the main reason is that yttrium has larger atom radius would let TiO2 maintain in amorphous phase. Hence, after annealed TiO2/Y2O3 shows higher capacitance density but TiO2 stays in amorphous state at the same time.
    Due to capacitance density and VCC-α has an inverse relationship, so we need to utilize another way called “canceling effect” of VCC-α. Canceling effect is achieved by two different oxide films, one has positive VCC-α and another one has negative VCC-α. Compare to adopt only one oxide film, once stack these two oxide films the effective VCC-α will become smaller due to positive VCC-α and negative VCC-α compensates each other. Furthermore, by utilizing the crystalline TiO2 to get higher capacitance density, but the VCC-α will become larger rapidly at the same time. To reduce the VCC-α, nitrogen plasma treatment on the surface of crystalline TiO2 was adopted; moreover, to further suppress the VCC-α, SiO2 is stacked on the crystalline TiO2 because of SiO2 has negative VCC-α that can compensate the positive VCC-α introduced by crystalline TiO2. In this work, MIM capacitor shows 30 ppm/V2 of VCC-α, 11.2 fF/μm2 of capacitance density, these results fit the requirements of MIM capacitor in 2018 by ITRS. But compare to novel metal oxide, SiO2 has much lower dielectric constant (κ) value, so the next part is replacing SiO2 to ZrTiOx.
    It is worth to mention that ZrTiOx demonstrates negative VCC-α characteristic like SiO2, but has much higher κ value, 22.5. Thus, the results of this work we got a much higher capacitance density of 14.38 fF/μm2 and 68 ppm/V2 of VCC-α.
    In the RRAM topic, we spent lots of effort to discuss how the property of ZrTiOx affects the electrical characteristics of RRAM. First, we explored the influence of crystalline ZrTiOx compared to amorphous one. Second, we examined how the position of IL effects switching mechanism, based on this, we planned three experiments each has different IL position, one has no IL, another has an IL on the bottom electrode and the last one has IL on the both top and bottom electrode. In this series experiments, we found that amorphous ZrTiOx demonstrates better uniformity, lower switching voltage, faster switching speed and larger sense margin; on the other hand, the position of IL is a critical factor that affects switching voltage, thus, IL could be modulated to achieve higher switching speed and better power consumption. In summary, one-sided IL shows better electrical characteristics.
    In addition, if we want to achieve higher storage capacity, 3D stack structure is an inevitable solution; however, to avoid the misread situation due to unexpected current flow, for one RRAM device we need another diode to form a 1D1R structure. In this work, we combined a simple metal-semiconductor diode and a RRAM to a TaN/ZrTiOx/Ni/n+-Si structure, the advantages are following, first, this structure is compatible with the incumbent ULSI technology; second, reduced the cost due to discard the expensive and hardly processing metal, such as W and Pt. Additionally, this structure is combined the one-sided IL formation that will further improve the electrical characteristics of RRAM.

    摘要 i Abstract iii Acknowledgement/Preface v Contents vi List of Tables viii List of Illustrations ix List of acronyms xiv Chapter 1 1 Introduction 1 1.1 Background 1 1.2 Motivation 10 Chapter 2 17 Advanced MIM Capacitor 17 2.1 Introduction 17 2.2 Using Stacked TiO2/Y2O3 as Insulator 22 2.3 Using Crystalline-TiO2/SiO2 Stack as Insulator 30 2.4 Effect of NPT on Crystalline-TiO2/SiO2 Insulator 37 2.5 NPT on ZrLaOx/ZrTiOx/ZrLaOx Insulator 46 Chapter 3 52 RRAM 52 3.1 Introduction 52 3.2 Impact of Dielectric Crystallinity on RRAM 55 3.3 Impact of Interfacial Layer on RRAM 64 Chapter 4 75 1D1R RRAM 75 4.1 Introduction 75 4.2 Rectifying Characteristics by Integrating Ni/n+-Si Diode 77 Chapter 5 88 Conclusion 88 5.1 MIM Capacitor 88 5.2 RRAM 89 References 91 Publication List 101

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