研究生: |
楊智勛 Chih-Hsun Yang |
---|---|
論文名稱: |
應用於無線都會區域網路之3.5GHz互補式金氧半射頻前端電路 A 3.5GHz CMOS RF Front-end for WiMAX Applications |
指導教授: |
柏振球
Jenn-Chyou Bor |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2007 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 81 |
中文關鍵詞: | 射頻前端電路 、低雜訊放大器 、混頻器 |
外文關鍵詞: | RF front-end, LNA, Mixer |
相關次數: | 點閱:4 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文中,2個應用於無線都會區域網路(WiMAX)的互補式金氧半射頻前端電路會被提出並且驗證呈獻。這些電路都是在TSMC 0.18 微米單多晶層六金屬層之互補式金氧半場效電晶體製程來設計實現的,並且可以應用在能高度整合的直接降頻式接收器上。
在第一個射頻前端電路中,使用了負阻式的負載以增加增益和雜訊的表現。除此之外,還有一個直流偏移量的減低迴路是要用來解決直流偏移量所產生的問題。藉由量測結果的驗證可知,這個射頻前端電路有著11 dB的電壓轉換增益(CG),-27.5 dBm 的1dB增益下降點(P1dB),-14 dBm 的三階項截取點(IIP3),23 dBm 的二階項截取點(IIP2),和6.13 dB的雜訊指數(NF)。電路的總功率消耗為35.3毫瓦,而且是操作在1.8伏特的電壓下,面積大小是1000微米乘上998微米。在直流偏移量的減低迴路的幫助之下,此射頻前端電路輸出端的直流偏移量可以小於6 毫伏特,並且可以改善6 dBm的二階項截取點。
在第二個射頻前端電路中,增加了一個降低flicker雜訊的電路以改善在頻率較低時的雜訊表現。從模擬結果可得知,這個射頻前端電路有著33.68 dB的電壓轉換增益,-33.7 dBm 的1dB增益下降點,和一個近乎平坦的雜訊指數曲線。舉例來說,藉由模擬結果可以得知,在10 KHz點的雜訊指數可以有著13.8 dB的改善量。電路的總功率消耗為33.1毫瓦,而且是操作在1.8伏特的電壓狀況之下。
In this thesis, two CMOS RF front-end circuits are proposed for WiMAX applications. These circuits are realized in TSMC 0.18 um 1P6M CMOS process technology can be applied to direct conversion receivers for high integration.
For the first RF front-end circuit, the negative-resistance loading are used to increase the gain and the noise performance. Moreover, there is a DC-offset cancellation loop to solve the DC-offset problem. According to the measurement results, the RF front-end has a voltage conversion gain (CG) of 11 dB, a 1-dB gain compression point (P1dB) of -27.5 dBm, an input third-order intercept point (IIP3) of -14 dBm, an input second-order intercept point (IIP2) of 23 dBm, and a noise figure (NF) of 6.13 dB. The power consumption is 35.3 mW from a 1.8 V supply and its area is 1 mm2. With the help of the DC-offset cancellation loop circuits, the output DC-offset is smaller than 6 mV and the IIP2 improvement is 6dBm.
For the second circuits, a flicker-noise reduction circuit is added to increase the low-frequency noise performance. The simulation results show that this RF front-end has a voltage conversion gain of 33.68 dB, a 1-dB compression point of -33.7 dBm, and a flat noise figure curve. From the simulation results, the improvement of NF at 10 KHz is 13.8 dB. It dissipates 33.1 mW from a 1.8 V supply.
[1] IEEE Standard for Local and Metropolitan Area Networks Part 16Air Interface for Fixed Broadband Wireless Access Systems, IEEE Std 802.16-2004 (Revision of IEEE std 802.16-2001).
[2] B. Razavi, RF Microelectronics, Prentice-Hall, Upper Saddle River, 1998.
[3] Samavati, H.; Rategh, H.R.; Lee, T.H., “A 5-GHz CMOS wireless LAN receiver front end,” IEEE J. Solid-State Circuit, vol. 35, pp. 765-772, May. 2000.
[4] Shaeffer, D. K. ; Lee, T. H., “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuit, vol. 32, pp. 745-759, May. 1997.
[5] B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.
[6] Munusamy, Kumar; Yusoff, Zubaida, “A Highly Linear CMOS Down Conversion Double Balanced Mixer,” IEEE International Conference on Semiconductor Electronics, pp. 985-990, Dec. 2006.
[7] Sedra Smith, Microelectronic Circuits, fifth edition, Oxford University Press, 2004.
[8] Behbahani, F.; Kishigami, Y.; Leete, J.; Abidi, A.A., “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, pp. 873-887, Jun. 2001.
[9] J. C. Bor “Experiments of Basic Circuit Theory” Lecture Slides.
[10] B. Razavi, “Design Considerations for Direct Conversion Receiver,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 428–435, June 1997.
[11] D. Coffing and E. Main, “Effects of offsets on bipolar integrated circuit mixer even-order distortion terms,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 23–30, Jan. 2001.
[12] B. Razavi, Design of analog CMOS Integrated Circuits, McGraw Hill International Edition 2001, Singapore.
[13] D. Manstretta, R. Castello, and F. Svelto, “Low 1/f noise CMOS active mixers for direct conversion,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 846–850, Sept. 2001.
[14] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: A simple physical model,” IEEE J. Solid-State Circuits, vol. 35, pp. 15–25, Jan. 2000.
[15] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. 11, vol. 44, pp. 428-435, June 1997.
[16] Tuan-Anh Phan; Chang-Wan Kim; Min-Suk Kang; Sang-Gug Lee; Chun-Deok Su, “Low noise and high gain CMOS down conversion mixer,” International Conference on Communications, Circuits and Systems, vol. 2, pp. 1191-1194 June 2004.
[17] H. Darabi and Chiu, J, “A noise cancellation technique in active RF-CMOS mixers,” IEEE J. Solid-State Circuits, vol. 40, pp. 2628–2632, Dec. 2005.
[18] K. Kivek□s, A. P□rssinen, and K. A. I. Halonen, “Characterization of IIP2 and DC-offset in transconductance mixers,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 1028–1038, Nov. 2001
[19] K. Kivek□s, A. P□rssinen, J. Ryyn□nen, J. Jussila, K. Halonen, “Calibration Techniques of Active BiCMOS Mixers,” IEEE J. Solid-State Circuits, vol. 37, pp. 766-769, June 2002.
[20] B. Razavi, and Bruce A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916–1926, Dec. 1992.