中文摘要
隨著可攜式低功率電子產品的需求越來越大，利用電源管理來延長電池壽命，已經成為一種趨勢。低壓降穩壓器由於有良好的暫態響應、較小的輸出雜訊以及較小的晶片面積，已成為電源管理技術中一個不可或缺的元件。然而低壓降穩壓器在設計上仍然有一些未能克服的問題，如過低的效率，難以整合以及穩定性問題。因此，本篇論文將會介紹低壓降穩壓器在設計上的挑戰，並提出兩種新式的補償架構來解決所面臨的問題。
首先，會介紹一些關於低壓降穩壓器的基本名詞與原理。接著提出一個以電壓控制電流源為基礎的低壓降穩壓器，利用電壓控制電流源來做頻率補償可以有效的改善暫態響應，容忍較大的電容寄生電阻值，此外此架構只需消耗的少量的靜態電流。
對於系統單晶片的實現上，額外的輸出電容是一項阻礙。所以，提出了一個整合式低壓降穩壓器，並且額外附加能夠改善暫態響應的電路。此架構在有無外接電容兩種情況下，都能夠維持穩定操作，詳細的數學模型分析將一同附上。本架構還包含一個動態轉導補償電路，可以保證低壓降穩壓器在零輸出電流的情況下也不會造成系統的不穩定。此外，電路中包含了一個暫態充放電的機制，能在迴路還來不及反應之前，先提供一些緩衝電流，藉以減緩輸出電壓的瞬間變化。

Abstract
As the larger requirement for low power portable electronic devices, power management becomes a popular solution for extending the battery life. Low dropout regulator (LDO) is a fundamental block of power management due to better load transient response, small output voltage ripples, and small area. However, it still suffers form some problems such as low efficiency, stability, and hard to integrate. Therefore, this thesis will introduce the design challenge of LDO regulators and proposed two compensation schemes to solve these problems.
First, we will introduce some terms, definitions, fundamental concepts and design considerations about the LDO regulator. Next, we propose a frequency compensation scheme for LDO regulator by a novel voltage control current source (VCCS). This LDO occupies lower quiescent current, have better transient response, and can extend the stable region of different ESR value of output capacitor.
Next, a capacitor-free LDO regulator with transient response enhancement is proposed. This LDO regulator can operate whether an off-chip output capacitor is added or not and the stable region is extended. The detailed mathematic analysis is described clearly. In addition, a dynamic gm boosting block is presented to maintain the stability even with zero output loading condition. A slew rate enhancement circuit is proposed to reduce the voltage dips when a large output current loading increasing suddenly.

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