近年來，可攜式的個人娛樂產品和可攜式的健康照顧的儀器越來越多，而人體通訊網路(BAN)能讓這些產品及儀器使用的更方便和發揮最好的應用效果。BAN是無線和短距離的通訊系統。人體通道傳輸(HBC)是BAN中其中一種傳輸方法。HBC可以達到低能源消耗、高資料傳輸速率和能在好的SNR下操作。

在此論文中，HBC收發器被提出並且介紹人體通道的特性。HBC是利用電場傳輸技術經由人體傳送訊號。人體通道就像帶通的濾波器由1MHz到100MHz和導體一般有高於空氣300到500倍的介電系數，因此人體被用來當作傳輸媒介。而人體通道有兩個主要的方向被大家討論，一個是頻率響應，它包含振福和相位的變化；另一個是雜訊特性，它包含60Hz能源線的影響和其他無線電波的干擾。

論文中所提出的HBC系統操作的頻帶是18.375 MHz到23.625MHz並且利用frequency selective (FS)調變方法，而最高的資料傳輸速率是1.3125Mbps。整個系統的時脈是42MHz而中心頻率是21MHz。傳送端利用frequency selective digital transmission (FSDT)的方法和電極貼片來傳送訊號，因此不需要使用天線和一些RF元件。接收端包含訊號偵測、取樣點偵測時間同步和時脈飄移，並操作在84MHz下。功能上的模擬和實驗的結果都驗證了演算法的可行性並且顯示系統的成效。基於AWGN和實驗的通道結果，當傳送128byte的封包和傳輸速率為1.3125Mbps時，模擬的結果可以達到封包錯誤率低於10-2時SNR為-1.8dB。整個系統架構和邏輯設計都會在此論文中提出。而邏輯設計的驗證是利用FPGA實驗版。

Body area network (BAN) is a solution for wearable personal entertainments and wearable healthcare. BAN is a wireless and short-range communication system. The human body communication (HBC) is one of the transmission technologies of BAN. HBC achieves low power consumption, high data rate and operating with good signal-to-noise ratio (SNR).

In this thesis, we propose a transceiver of HBC and introduce the human body channel. The HBC system uses the electric field communication technology to transmit signal through human body. The human body channel is similar to a band-pass filter from 1 MHz to 100 MHz and a conductor which has 300 to 500 times better permittivity than air. Hence, human body is used as a transmission medium and is discussed in two parts. The frequency response which
includes the change of amplitude and phase. And the noise characteristics which includes 60 Hz power-line noise and interferences of other devices.

The proposed design of HBC system employs the bandwidth from 18.375 MHz to 23.625 MHz and supports the frequency selective (FS) spreader modulation scheme with maximum
data rate of 1.3125 Mbps. The whole system is operating in 42 MHz frequency clock and 21 MHz frequency center. The transmitter uses the frequency selective digital transmission(FSDT) scheme so it doesn’t need mixer and RF device. The receiver contains packet detection, sample point detection, timing synchronization and clock drift synchronization with 84 MHz sampling rate. Functional simulations and experiments show the validity of these
algorithms and system performance of the proposed transceiver. Under AWGN noise and the channel of experiment result scenario, the simulation results show that the packet error rate(PER) is less than 10−2 in SNR -1.8 dB with a payload of 128 octets and 1.3125 MHz data rate.
The architecture and logic design of proposed receiver are also presented. The functionality of proposed logic design is verified by FPGA emulation.

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