本篇論文提出一個供 Openflow 交換器使用的快取設計。我們以硬體來實作交換器的路由並用軟體來實作搜尋引擎。藉由分析國立清華大學計算機通訊中心的網路流量資料，我們觀察到網路封包和交換器的連接埠之間存在空間局部性。我們提出了一個各別連接埠快取的設計來妥善利用此空間局部性。這個設計以Verilog語言和C語言實作的搜尋引擎來實作。我們以不同的快取配置、網路流量和網路拓撲來測試我們的設計原型。和常用的軟體交換器 - Open vSwitch相比，我們的設計可以用相當少的成本來增加交換器的效能。

We propose a cache design for an OpenFlow switch which implements datapath in hardware and search engine in software.
By analyzing some of National Tsing Hua University traffic records from the Computer and Communication Center, we observe that flows and switch ports exhibit spatial locality.
We propose a per-port cache design to take advantage of those spatial locality.
The design is implemented in Verilog together with a C-based search engine.
We evaluate our prototype with various cache configurations, traffic patterns and topologies.
Compared with a popular software Open vSwitch , our per-port cache design improves switch performance with little overhead.

[1] \Software-dened networking," Available at https://www.opennetworking.org/
images/stories/downloads/sdn-resources/white-papers/wp-sdn-newnorm.
pdf.
[2] N. Gude, T. Koponen, J. Pettit, B. Pfa, M. Casado, N. McKeown, and S. Shenker,
\Nox: Towards an operating system for networks," SIGCOMM Comput. Commun.
Rev., vol. 38, pp. 105{110, July 2008.
[3] D. Erickson, \The beacon open
ow controller," in Proceedings of the Second ACM
SIGCOMM Workshop on Hot Topics in Software Dened Networking, HotSDN '13,
(New York, NY, USA), pp. 13{18, ACM, 2013.
[4] \Floodlight," Available at http://www.projectfloodlight.org/floodlight/.
[5] M. Jarschel, S. Oechsner, D. Schlosser, R. Pries, S. Goll, and P. Tran-Gia, \Modeling
and performance evaluation of an open
ow architecture," in Teletrac Congress
(ITC), 2011 23rd International, pp. 1{7, Sept 2011.
[6] A. Bianco, R. Birke, L. Giraudo, and M. Palacin, \Open
ow switching: Data plane
performance," in Proceeding of the 2010 IEEE International Conference on Com-
munications (ICC), pp. 1{5, May 2010.
[7] \Open
ow switch specication," Available at https://www.opennetworking.org/
images/stories/downloads/sdn-resources/onf-specifications/openflow/
openflow-spec-v1.3.0.pdf.
[8] J. Naous, D. Erickson, G. A. Covington, G. Appenzeller, and N. McKeown, \Im-
plementing an open
ow switch on the netfpga platform," in Proceedings of the
4th ACM/IEEE Symposium on Architectures for Networking and Communications
Systems, ANCS '08, (New York, NY, USA), pp. 1{9, ACM, 2008.
[9] B. Pfa, J. Pettit, T. Koponen, K. Amidon, M. Casado, and S. Shenker, \e.a.:
Extending networking into the virtualization layer," in Procedings of the 8th ACM
Workshop on Hot Topics inNetworks (HotNets-VIII), New YorkCity, NY,October
2009.
[10] \What are white box switches?," Available at https://www.sdxcentral.com/
resources/white-box/what-is-white-box-networking/.
[11] M. Zec, L. Rizzo, and M. Mikuc, \Dxr: Towards a billion routing lookups per
second in software," SIGCOMM Comput. Commun. Rev., vol. 42, pp. 29{36, Sept.
2012.
[12] Y. Luo, P. Cascon, E. Murray, and J. Ortega, \Accelerating open
ow switching
with network processors," in Proceedings of the 5th ACM/IEEE Symposium on
Architectures for Networking and Communications Systems, ANCS '09, (New York,
NY, USA), pp. 70{71, ACM, 2009.
[13] V. Tanyingyong, M. Hidell, and P. Sjodin, \Improving pc-based open
ow switching
performance," in 2010 ACM/IEEE Symposium on Architectures for Networking
and Communications Systems (ANCS), pp. 1{2, Oct 2010.
[14] V. Tanyingyong, M. Hidell, and P. Sjodin, \Using hardware classication to improve
pc-based open
ow switching," in 2011 IEEE 12th International Conference on High
Performance Switching and Routing (HPSR), pp. 215{221, July 2011.
[15] \Engineered elephant
ows for boosting application performance in large-
scale clos networks," Available at https://www.broadcom.com/collateral/wp/
OF-DPA-WP102-R.pdf.
[16] \Tcam," Available at https://en.wikipedia.org/wiki/Content-addressable_
memory#Ternary_CAMs.
[17] T. Chiueh and P. Pradhan, \Cache memory design for network processors," in
Proceedings. Sixth International Symposium on High-Performance Computer Ar-
chitecture, 2000. HPCA-6, pp. 409{418, 2000.
[18] D. E. Thomas and P. R. Moorby, The Verilog Hardware Description Language, 5th
Edition. Norwell, MA, USA, Kluwer Academic Publishers, 2002.
[19] \NetFPGA 10G Reference NIC", Available at https://github.com/NetFPGA/
NetFPGA-public/wiki/NetFPGA-10G-Reference-NIC.
[20] \Introduction to pci protocol," Available at http://electrofriends.com/
articles/computer-science/protocol/introduction-to-pci-protocol/.
[21] \Modelsim," Available at http://www.mentor.com/products/fv/modelsim/.
[22] \Ubuntu," Available at http://www.ubuntu.com/download/desktop.
[23] \Systemverilog," Available at http://standards.ieee.org/getieee/1800/
download/1800-2012.pdf.
[24] \Tun/tap," Available at https://en.wikipedia.org/w/index.php?title=TUN/
TAP&redirect=no.
[25] B. Lantz, B. Heller, and N. McKeown, \A network in a laptop: Rapid prototyping
for software-dened networks," in Proceedings of the 9th ACM SIGCOMM Work-
shop on Hot Topics in Networks, Hotnets-IX, (New York, NY, USA), pp. 19:1{19:6,
ACM, 2010.
[26] \Pox," Available at http://www.noxrepo.org/pox/about-pox/.
[27] \Ripcord-lite for pox: A simple network controller for open
ow-based data cen-
ters.," Available at https://github.com/brandonheller/riplpox.
[28] M. Al-Fares, S. Radhakrishnan, B. Raghavan, N. Huang, and A. Vahdat, \Hed-
era: Dynamic
ow scheduling for data center networks," in Proceedings of the 7th
USENIX Conference on Networked Systems Design and Implementation, NSDI'10,
(Berkeley, CA, USA), pp. 19{19, USENIX Association, 2010.
[29] \ping," Available at http://linux.die.net/man/8/ping.
[30] \Iperf," Available at https://iperf.fr/.
[31] T. Benson, A. Anand, A. Akella, and M. Zhang, \Understanding data center trac
characteristics," SIGCOMM Comput. Commun. Rev., vol. 40, pp. 92{99, Jan. 2010.