在本篇論文裡，我們去歸納「再使用之距離」的分析方法，並且用來發展一套有效率而且有實用性地去探索多層快取記憶體的最佳化結果的方法。針對快取記憶體的大小、成本、功耗、或者平均存取資料的延遲等最佳化問題，我們採用簡單的掃描式搜索來找到上述所列的問題的最佳解。而我們提出的方法比過去傳統用模擬的方式經驗證後顯示快上150~250倍不等，因此對於系統設計者在設計初期是非常有用的。此外，我們也提出一個簡單的分析式模型來提供系統設計者了解快取記憶體的設計參數是如何影響最佳化的結果。因此系統設計者能夠在系統設計的早期階段就能夠對最佳化的設計方相作出一個適當的設計目標走向。

In this paper we generalize the reuse distance analysis method and develop an effective and practical multi-level cache design optimization approach. We adopt a simple scanning search method to locate optimal cache solution in terms of cache size, power consumption or average data access delay. The proposed approach is particularly useful for early-phase system designers and is verified to be 150 to 250 times faster than the traditional simulation-based approach and. In addition, we also propose a simplified analytical model and provide designers insights about how cache design parameters may affect the expected results. As a result, designers can make adequate decision at early system design phase.

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