在現代技術演進的格局中，由於固有的物理限制，對不停縮小電晶體大小的過程中遇到了巨大的障礙，使得摩爾定律十分難以達成。 然而，三維晶片封裝技術的誕生正迎來新的機會篇章。然而現行的許多三維晶片設計的擺放研究大多是使用二維近似的擺放與繞線流程改良而來，針對三維晶片設計的實際應用仍然缺乏。本篇論文的主要想法是針對有兩個晶片的三維晶片設計，在輸入資料中尚未決定實例的應被放到哪個晶片上，透過我們提出的分割方式，不僅能符合晶片利用度的限制，也能影響後續步驟有更低的線長表現，實驗結果中也證明我們的方法有效。另外，在三維晶片擺放後，針對可移動的巨集，我們也提出一個整數線性規劃巨集合法化方法，相較於模擬退火基礎的巨集合法器，不僅更加可靠，實驗結果中也表明線長相較模擬退火的方法有2.4%的減少。

In modern technological evolution, reducing transistor sizes has encountered significant challenges due to inherent physical limitations, making it exceedingly difficult to realize Moore's Law. However, the advent of 3D packaging technology is opening up new possibilities and directions. Despite this, many studies on 3D-IC design placement mainly adapt improvements from 2D place and route flow, leaving a void in practical applications for 3D-IC design. The primary objective of this work is to address this gap by focusing on a face-to-face 3D-IC design. Before determining the partition for the input instances, our proposed partitioning method not only complies with the die utilization constraints but also facilitates a lower wirelength in subsequent stages, as showed by experimental results demonstrating the efficacy of our approach. Furthermore, following the 3D-IC global placement, an ILP macro legalization method for movable macro is introduced. This method is a more reliable alternative to the simulated annealing-based macro legalizer, showing a reduction of 2.4% in wirelength compared to the SA technique.

[1] M. A. Bolanos, “3d packaging technology: Enabling the next wave of applications,” in
2010 34th IEEE/CPMT International Electronic Manufacturing Technology Symposium
(IEMT), pp. 1–5, 2010.
[2] C. Fiduccia and R. Mattheyses, “A linear-time heuristic for improving network partitions,”
in 19th Design Automation Conference, pp. 175–181, 1982.
[3] S. S. Kiran Pentapati, K. Chang, V. Gerousis, R. Sengupta, and S. K. Lim, “Pin-3d: A
physical synthesis and post-layout optimization flow for heterogeneous monolithic 3d ics,”
in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–
9, 2020.
[4] B. W. Ku, K. Chang, and S. K. Lim, “Compact-2d: A physical design methodology to build
two-tier gate-level 3-d ics,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 39, no. 6, pp. 1151–1164, 2020.
[5] S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Shrunk-2-d: A physical design methodology
to build commercial-quality monolithic 3-d ics,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 36, no. 10, pp. 1716–1724, 2017.
[6] S. Panth, K. Samadi, Y. Du, and S. K. Lim, “Placement-driven partitioning for congestion
mitigation in monolithic 3d ic designs,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 34, no. 4, pp. 540–553, 2015.
[7] J.-M. Lin, P.-C. Lu, H.-Y. Lin, and J.-T. Tsai, “A novel blockage-avoiding macro place-
ment approach for 3d ics based on pocs,” in 2022 IEEE/ACM International Conference
On Computer Aided Design (ICCAD), pp. 1–7, 2022.
[8] D. H. Kim, K. Athikulwongse, and S. K. Lim, “Study of through-silicon-via impact on
the 3-d stacked ic layout,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 21, no. 5, pp. 862–874, 2013.
[9] S. M. Sait, F. C. Oughali, and M. Al-Asli, “Design partitioning and layer assignment for
3d integrated circuits using tabu search and simulated annealing,” Journal of Advanced
Research, pp. 67–76, 2015.
[10] J. Lu, H. Zhuang, I. Kang, P. Chen, and C.-K. Cheng, “Eplace-3d: Electrostatics based
placement for 3d-ics,” in Proceedings of the 2016 on International Symposium on Phys-
ical Design, ISPD ’16, (New York, NY, USA), p. 11–18, Association for Computing
Machinery, 2016.
27
[11] G. Luo, Y. Shi, and J. Cong, “An analytical placement framework for 3-d ics and its exten-
sion on thermal awareness,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 32, no. 4, pp. 510–523, 2013.
[12] M.-K. Hsu, Y.-W. Chang, and V. Balabanov, “Tsv-aware analytical placement for 3d ic
designs,” in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 664–
669, 2011.
[13] Gurobi Optimization, LLC, “Gurobi Optimizer Reference Manual,” 2023.
[14] I.-J. L. Y.-H. W. W.-H. C. Kai-Shun Hu, Hao-Yu Chi and Y.-T. Hsieh, “2023 iccad cad
contest problem b: 3d placement with macros.,” 2023 ICCAD CAD Contest Problem B.,
2023.
[15] C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “Replace: Advancing solution quality
and routability validation in global placement,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2019.
[16] P. Spindler, U. Schlichtmann, and F. M. Johannes, “Abacus: Fast legalization of standard
cell circuits with minimal movement,” in Proceedings of the 2008 international sympo-
sium on Physical design, pp. 47–53, 2008.
[17] T.-C. Chen and Y.-W. Chang, “Modern floorplanning based on b*-tree and fast simulated
annealing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sys-
tems, vol. 25, no. 4, pp. 637–650, 2006.