由於元件縮小化、電漿不均勻性、以及高介電係數閘極介電層的考量，使得電漿充電所致損害依然是金氧半元件製程中的關鍵課題。首先，氧化層厚度的縮小至其電流傳導機制為直接穿隧(direct tunneling)時，其電漿充電所致損傷可能會減輕。再者，利用並聯二極體(shunt diode)於閘極上，可測得電漿不均勻所致的充電極性：在高密度電漿機台中，晶圓中心附近呈現正電荷累積；反之，晶圓邊緣則呈現負電荷累積。另外，閃動雜訊(flicker noise)能有效地反映出電漿充電損害所導致之界面陷阱(interface trap)情形：界面陷阱的增加會增大所測得之閃動雜訊。最後，元件蝕刻後，將其額外暴露於純電漿中，可大幅減輕因電漿蝕刻製程所導致的元件電特性率退現象。在減低電漿充電效應方面，相較於傳統的氮化氧化層，利用兩階段氮化處理(two-step nitridation)之氮化氧化層，搭配非晶矽閘電極(amorphous silicon)，能更有效地減低電漿充電導致之電特性及可靠度衰退情形：其原因在於非晶矽閘電極有助於界面應力的紓解，以及第二階段氮化處理可減低有害元素的擴散至閘極氧化層。在高介電係數閘極介電層(Si3N4 , Ta2O5)之電漿充電效應方面，堆疊(stacked)的閘極結構在低電場之下的較低閘極漏電流特性雖可歸因於緩衝層(buffer layer)的介入，但其電漿充電效應之下的電性衰退並未明顯改善，且其終究受限於元件厚度的縮小化；而在單層(single layer)的閘極結構方面，氮化矽(Si3N4)閘極介電層因其漏電較大且其元件之崩潰時間太短，而暴露其可靠度的問題；而五氧化二鉭(Ta2O5)閘極介電層因其電流傳導機制與陷阱(trap)有極大關係，因而較厚之五氧化二鉭薄膜對電漿充電所致損傷較敏感。

Plasma charging induced damage on gate dielectrics of MOS devices is an important issue in terms of shrinking dimension, plasma non-uniformity and effects on high-k gate dielectrics. A comprehensive study of plasma charging effects on the electrical properties of MOS devices was investigated in this thesis. Scaling effect of gate oxide thickness shows that the electrical property degradation induced by plasma charging damage may be slight as gate oxide thickness scales down into direct tunneling regime. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma charging damage. Extra exposure to plasma ambient can greatly reduce the plasma charging induced damage, which can be attributed to photo-annealing. For reinforcing the robustness of gate dielectrics, gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interfacial strain by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. For alternative gate dielectric in the future application, plasma-charging damage on Si3N4 and Ta2O5 gate dielectrics with high dielectric constant was also investigated. In the stacked gate dielectrics, such as Ta2O5/oxynitride and Ta2O5/Si3N4, the mixed effect of the buffer layer (oxynitride or Si3N4) and Ta2O5 film works well in low electrical field region. Yet it doesn’t show any significant reduction in plasma charging induced electrical degradation and eventually limits the thickness scaling. For MOS devices with Si3N4 gate dielectric, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta2O5 gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta2O5 film more susceptible to plasma charging induced damage.

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