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研究生： 陳奕儒
Chen, Yi-Ju
論文名稱： 使用分層位元線轉向控制方案之6T轉置靜態隨機存取記憶體
A 6T Transpose SRAM using Hierarchical-Bitline-Steering Control Scheme
指導教授： 張孟凡
Chang, Meng-Fan
口試委員: 許世玄
Sheu, Shyh-Shyuan
呂仁碩
Liu, Ren-Shuo
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 106
語文別： 英文
論文頁數： 59
中文關鍵詞： 靜態隨機存取記憶體 、轉置 、分層位元線
外文關鍵詞： Static Random Access Memory, Transpose, Hierarchical-Bitline
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    • 新興的人工智慧類神經網路演算法使特殊記憶體和近記憶體計算、記憶體內計算設計成為吸引人的研究主題。這類的特殊記憶體通常在系統中扮演硬體加速器的角色，為系統帶來更高性能或更低功耗。
    轉置存取記憶體是特殊記憶體的一類，並且在電腦矩陣運算，二維影像處理以及人工智慧類神經網路中被廣泛應用。轉置存取記憶體能夠以不同的方向讀寫存儲的資料，從而降低了上述應用的設計和操作複雜性。
    在此作品，我們提出了一使用分層位元線轉向控制方案之6T轉置靜態隨機存取記憶體，通過使用區域I / O電路實現轉置讀取和寫入，將局部位元線引導連接至不同方向的全域位元線。此6T轉置靜態隨機存取記憶體提供了首次能與邏輯記憶體製程相容的解決方案，這使得我們的設計可以實現比其他需要客制化記憶體單元更小的面積，且能保證高良率。
    透過六十五奈米互補式金氧半邏輯製程技術，建構出一容量為六十四千字元之分層位元線轉向控制方案之6T轉置靜態隨機存取記憶體。藉由量測，此晶片可於一伏特之操作電壓下達到0.8奈秒的讀取速度，且操作電壓最低可達到四百毫伏特。這個作品之品質因數:(操作速度)除以(巨集面積乘以消耗能量) 達到其他轉置存取記憶體之三倍以上。

    Recent trends on emerging AI neural network algorithms make special memory and near/in-memory computing designs become attractive research topic. This kind of feature memories acts as hardware accelerator and give high performance or low energy feature to the system.
    Transpose memory is one category of feature memories and has been widely employed in matrix multiplication in computer graphics, data processing algorithm in 2D image processing and AI neural network thanks to its ability to access stored data in orthogonal direction to reduce design and operation complexity of the above mentioned application.
    In this work, we propose a 6T transpose static random access memory using hierarchical-bitline-steering control scheme (HBS-TRAM). Proposed work is based on hierarchical bit-line structure, which achieves transpose read and write by using local I/O circuits to guide the local bit-lines to the global bit-lines in different directions. The HBS-TRAM 6T cell provides, for the first time, the solution to use the same footprint as foundry compact cell. This enables our transpose SRAM design to achieve a most small area than other customized SRAM cells without using aggressive layout rules for SRAM, guaranteeing small-area and high-yield on memory cells.
    A fabricated 65nm CMOS logic process 64Kb HBS-TRAM achieved 0.8ns access time at VDD=1.0V by oscilloscope testing. And working supply voltage can down to 0.4V. The figure of merit (FOM): [Speed]/[Macro-Area* Energy] is 3.1+x higher than that of other transpose SRAM design.

    國立清華大學 碩士論文 I 摘要 III Abstract IV 致謝 V Contents VI List of Figures VIII List of Tables X Chapter 1. Introduction 1 1.1 The Memory Landscape 1 1.1.1 RAM 3 1.1.2 CAM 4 1.1.3 ROM 5 1.1.4 Programmable NVMs 6 1.2 Transpose Memory Background 7 1.3 Overview of this thesis 8 Chapter 2. Design Challenges of SRAM 9 2.1 Introduction for Conventional 6T SRAM 9 2.1.1 Static Noise Margin of 6T SRAM Cell 10 2.1.2 Write Margin of 6T SRAM Cell 12 2.2 Cell Stability Issue of Conventional 6T SRAM 13 2.2.1 Read Disturb and Half-Select Disturb 13 2.2.2 Trade-off between WM and HS-SNM 15 2.3 Design Considerations of Conventional Write-Assist Techniques 16 2.3.1 Common Write-Assist Techniques 16 2.3.2 Challenge of Common Write-Assist Techniques 18 Chapter 3. Introduction of Transpose Memory 20 3.1 Application of Transpose Memory 20 3.2 Published Transpose Memory Schemes 22 3.2.1 7T Transpose-Read SRAM (KAIST) 22 3.2.2 8T Transpose SRAM (IBM) 24 3.2.3 10T Transpose SRAM (TOSHIBA) 25 Chapter 4. Proposed Hierarchical-Bitline-Steering Control Transpose SRAM (HBS-TRAM) 26 4.1 Architecture of Proposed HBS-TRAM 26 4.1.1 Hierarchical-Bitline-Steering Scheme 27 4.1.2 6T Bit-cell Structure 30 4.1.3 Macro Structure 33 4.2 Operation of Proposed HBS-TRAM 35 4.2.1 Read and Write Operation in Normal Mode 35 4.2.2 Read and Write Operations in Transpose Mode 36 4.3 Analyses and Comparison 39 4.3.1 Area 39 4.3.2 Speed 41 4.3.3 Power Consumption 45 Chapter 5. Macro Implementation 48 5.1 Architecture of Proposed 6T HBS-TRAM Macro 48 5.2 Test Chip Design 50 Chapter 6. Experimental Results and Conclusion 51 6.1 Chip Performance Measurement 51 6.2 Thesis Summary and Conclusion 54 6.3 Future Works 56 Reference 56

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