近年來，智慧型手機、平板電腦、輕薄型筆記型電腦等3C產品日漸普及，進而影響了整個記憶體產業的市場，造成擁有低功率消耗、元件密度高、可攜式條件等特性的快閃記憶體的需求量大幅上升。然而，在元件日漸微縮的趨勢下，平面式元件微縮空間有限，造成元件密度難增且製程難度跟著大幅的提升，因此如何不損電性又要提高元件密度為目前最重要的課題之一。有些解決方法已漸漸被提出，如高介電常數材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用等等。本篇論文以無接面奈米線通道式快閃記憶體元件為主軸，輔以高介電常數材料作能帶工程的應用，加以研究並探討電性的表現。
第一個實驗首次將高介電常數和無接面作結合應用在快閃記憶體元件上。本實驗中，以二氧化鉿和具氧化鉿鋁/二氧化鉿堆疊的結構作為電荷捕捉層，製作在無接面奈米線通道式的快閃記憶體元件上，並與電荷反轉式奈米線通道式快閃記憶體元件做比較。無接面元件在寫入速度和可靠度特性的表現上都具有較佳的表現，唯抹除速度較電荷反轉式元件緩慢，而具氧化鉿鋁/二氧化鉿堆疊的結構也能有效提升元件的電荷保持力特性。
第二個實驗中以二氧化鉿/氮化矽堆疊的結構作為電荷捕捉層，製作在無接面奈米線通道式的快閃記憶體元件上，並與電荷反轉式奈米線通道式快閃記憶體元件做比較。無接面元件仍維持了較佳的寫入速度和可靠度特性，且在抹除速度方面也能有所提升，和電荷反轉式元件已可相互比擬。
第三個實驗研襲第二章使用的電荷捕捉層，並與普遍較為常見的氮化矽作電荷捕捉層，同樣的製作在無接面奈米線通道式的快閃記憶體元件上，並與電荷反轉式奈米線通道式快閃記憶體元件做比較。可以發現除了無接面元件仍維持較佳的電性表現外，堆疊式的電荷捕捉層也能對各種電性表現有改善的效果。

[1] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability,” Electron Devices, IEEE Transactions on, vol. 42, no. 1, pp. 150 –159, Jan 1995.

[2] M. White, D. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits and Devices Magazine,, vol. 16, no. 4, Jul 2000, pp. 22 –31.

[3] M. White, Y. Yang, A. Purwar, and M. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” in Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, Jun 1996, pp. 52 –57.

[4] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings, 2002. IEEE, vol. 5, 2002, pp. 5–2383 – 5–2390 vol.5.

[5] K. Kahng and S. Sze, “A floating gate and its application to memory devices,” Electron Devices, IEEE Transactions on, vol. 14, no. 9, p. 629, Sep 1967.

[6] A. Wang and W. D. Woo, “Static magnetic storage and delay line,” Journal of Applied Physics, vol. 21, no. 1, pp. 49 –54, Jan 1950.

[7] S. M. Sze and K. K. Ng, physics of semiconductor Devices, 3rdEd., Wiley Interscience, Hoboken, N.J. 2007.

[8] T. Y. Tseng and S. M. Sze, Eds, nonvolatile Memories Materials, Devices, and Applications, American Scientific Publishers, Stevenson Ranch, CA, 2012.

[9] White M. H., Adams D. A., and Bu J., “On the go with SONOS” IEEE Circuits Devices Mag., Vol. 16, No. 4, pp. 22-31, 2000.

[10] N. Yamauchi, J. J. Hajjar and R. Reif, "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Trans. Electron Devices, vol. 38, pp. 55-60, 1991.
[11] T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, Y. L. Wu, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig. 2007, pp. 913-916.

[12] M. Heyns, S. Beckx, H. Bender, P. Blomme, W. Boullart, B. Brijs, et al., "Scaling of high-k dielectrics towards sub-1nm EOT," in VLSI Technology, Systems, and Applications, 2003 International Symposium on, 2003, pp. 247-250.

[13] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-k metal-gate stack and its MOSFET characteristics," IEEE Electron Device Lett., vol. 25, pp. 408-410, 2004.

[14] S. C. Lai, H. T. Lue, M. J. Yang, J. Y. Hsieh, S. Y. Wang, T. Wu, G. L. Luo, C. H. Chien, E. K. Lai, K. Y. Hsieh, R. Liu and C. Lu, "MA BE-SONOS: A bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation," in Non-Volatile Semiconductor Memory Workshop, 2007, pp. 88-89.

[15] T. Yan-Ny, W. K. Chim, B. Jin Cho, and C. Wee-Kiong, "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer," Electron Devices, IEEE Transactions on, vol. 51, pp. 1143-1147, 2004.

[16] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. Chen, J. Ku, K. Y. Hsieh, R. Liu and C. Y. Lu, "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," in IEDM Tech. Dig. 2005, pp. 547-550.

[17] Z. H. Ye, K. S. Chang-Liao, T. C. Liu, T. K. Wang, P. J. Tzeng, C. H. Lin and M. J. Tsai, "A novel SONOS-type flash device with stacked charge trapping layer," Microelectron. Eng., vol. 86, pp. 1863-1865, 2009.

[18] J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. D. Akhavan, P. Razavi, R. Yan and R. Yu, "Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions," Sci. Adv. Mater., vol. 3, pp. 477-482, 2011.

[19] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, pp. 225-229, 2010.

[20] C. J. Su, T. K. Su, T. I. Tsai, H. C. Lin and T. Y. Huang, "A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires," Nanoscale Res. Lett., vol. 7, pp. 1-6, 2012.

[21] H. T. Lue, Y. H. Hsiao, P. Y. Du, S. C. Lai, T. H. Hsu, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, C. P. Lu, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, "A novel buried-channel FinFET BE-SONOS NAND flash with improved memory window and cycling endurance," in VLSI Symp. Tech. Dig. 2009, pp. 224-225.

[22] S. Tam, P.-K. Ko, and C. Hu, “Lucky-electron model of channel hot- electron injection in MOSFET’s,” Electron Devices, IEEE Transactions on, vol. 31, no. 9, pp. 1116 – 1125, Sep 1984.

[23] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings, 2002. IEEE, vol. 5, 2002, pp. 5–2383 – 5–2390 vol.5.

[24] M. H. White, Y. Yang, P. Ansha, and M. L. French, "A low voltage SONOS nonvolatile semiconductor memory technology," Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on, vol. 20, pp. 190-195, 1997.

[25] W. Tsai, N. Zous, C. Liu, C. Liu, C. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in Electron Devices Meeting, 2001. IEDM ’01. Technical Digest. International, 2001, pp. 32.6.1 –32.6.4.

[26] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability,” Electron Devices, IEEE Transactions on, vol. 42, no. 1, pp. 150 –159, Jan 1995.

[27] T. Yan-Ny, W. K. Chim, C. Wee Kiong, J. Moon-Sig, and B. Jin Cho, "Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation," Electron Devices, IEEE Transactions on, vol. 53, pp. 654-662, 2006.

[28] T. Ping-Hung, C.-L. Kuei-Shu, L. Chu-Yung, W. Tien-Ko, P. J. Tzeng, C. H. Lin, et al., "Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer," Electron Device Letters, IEEE, vol. 29, pp. 265-268, 2008.

[29] C. Sung-Jin, D.-I. Moon, J. P. Duarte, K. Sungho, and Y.-K. Choi, "A novel junctionless all-around-gate SONOS device with a quantum nanowire on a bulk substrate for 3D stack NAND flash memory," in VLSI Technology (VLSIT), 2011 Symposium on, 2011, pp. 74-75.

[30] T. Ping-Hung, C.-L. Kuei-Shu, L. Te-Chiang, W. Tien-Ko, T. Pei-Jer, L. Cha-Hsin, et al., "Charge-Trapping-Type Flash Memory Device With Stacked High-k Charge-Trapping Layer," Electron Device Letters, IEEE, vol. 30, pp. 775-777, 2009.

[31] Z. H. Ye, K. S. Chang-Liao, C. Y. Tsai, T. T. Tsai and T. K. Wang, "Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With Si3N4/Al2O3/HfO2 Charge-Trapping Layer," IEEE Electron Device Lett., vol. 33, pp. 1351-1353, 2012.

[32] J. P. Duarte, C. Sung-Jin, D.-I. Moon, and Y.-K. Choi, "Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors," Electron Device Letters, IEEE, vol. 32, pp. 704-706, 2011.

[33] Nasyrov K. A., Gritsenko V. A., Kim M. K., Chae H. S., Ryu W. I., Sok J. H., Lee J. –W., and Kim B. M., “Charge Transport Mechanism in Metal-Nitride-Oxide-Silicon Structures,” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 336-338, 2002.

[34] Y. Sun, H. Y. Yu, N. Singh, K. C. Leong, E. Gnani, G. Baccarani, G. Q. Lo, and D. L. Kwong, "Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity, " IEEE Trans. Electron Devices, vol. 58, pp. 1329-1335, 2011.