隨著現今半導體製程不斷的快速進步，元件中的最小線寬亦愈趨縮減，使得製程中所產生的製程變異影響更鉅。在積體電路量產之前，評估電路本身的效能是非常重要的，所以我們希望能對具有製程變異的layout進行分析。而要達到這個目的，首先要有一個光學微影模擬工具，於是我們使用我們實驗室已完成的光學微影模擬工具來幫助我們取得具有製程變異的layout。
在取得具有製程變異的layout後，我們希望能了解它在製程變異前後其路徑延遲(path delay)有何變化還有受到defect影響的差距多少。而要分析defect的影響，現行普遍的技術為關鍵區域分析(critical area analysis)，因此，在這篇論文裡我們參考了其他人的方法完成了一個關鍵區域分析軟體(critical area analysis tool)，並以此軟體來分析具有製程變異的layout。路徑延遲部分則依靠Calibre的電阻電容萃取(RC extraction)還有Hspice來分析。
然而因為光學微影模擬速度實在太慢，所以我們只能對cell和選取某些電路的critical path來作分析，而無法對整的電路進行分析。
論文最後我們會秀一下我們關鍵區域分析軟體的效能和結果，還有對有無製程變異的layout進行比較後發現：在cell延遲部分，因為transistor的Length受到製程變動後會顯著改變，延遲甚至高達原本的230%，路徑延遲部分則發現transistor受製程變動的影響比內部接線影響來的大，製成變異也將導致關鍵區域變大即代表錯誤發生機路較高狼率較低。

As the feature sizes in today’s semiconductor process keep shrinking, process variations have greatly influences on the performance of integrated circuits (ICs). Evaluating IC performance before mass production is quite important for quality control. The effects of process variations may result in inconsist circuit timing even for those die in the same wafer, resulting in tremendous yield loss. To know or estimate the extent of the timing variation for an IC before tapped-out which comes from process variations, we have to perform a more detailed simulation such as lithography simulation prior to manufacturing. Typically, these kinds of simulation are extremely slow, so the whole chip simulation is nearly impossible. In this thesis, we provide an alternative that could individually simulate and extract the timing of critical paths without performing whole chip simulation. Also, we have simulated a single cell’s timing variation under different conditions of optical aberrations, which can then be performed on cell based litho. simulation.
Besides of timing analysis, it is of equal importance to analyze the layout for locating the hot-spots in advance, which are susceptible to variations or spot defects. Critical area analysis (CAA) is a technique for this purpose that scans and analyzes a layout and reports the critical area for the layout. In this thesis, we will introduce the critical area analysis system that we implemented and use the system to analyze the layout with process variations before and after lithography simulation. With these two techniques, the hot-spots and critical portions of a layout can be identified and fixed at the design stage, shortening the development period for a new design.

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