MDSC相量估計技術於電力系統保護數位電驛的比較分析

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研究生：	莫翰拉傑 Mohanraj Bellie Subramani
論文名稱：	MDSC相量估計技術於電力系統保護數位電驛的比較分析 A Comparative Analysis of MDSC-Based Phasor Estimation Technique for Digital Relays in Power System Protection
指導教授：	朱家齊 CHU, CHIA-CHI
口試委員:	張淵智蘇昱丞吳有基連國龍黃維澤
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2025
畢業學年度：	113
語文別：	英文
論文頁數：	90
中文關鍵詞：	衰減直流分量、衰減直流分量、離散傅立葉變換、故障電流、諧波、相量估計
外文關鍵詞：	Decaying DC component, Decaying DC component, Discrete Fourier transform, Fault current, Harmonics, MDSC
相關次數：	點閱：2 下載：0
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衰減直流偏移(DDC) 對電力系統提出了重大挑戰，特別是在故障條件下，它會在故障電流波形中引入嚴重失真。這種失真使關鍵參數的可靠提取變得複雜，例如基頻分量的振幅和相位角，這對於保護繼電器的精確操作至關重要。DDC 的存在會延遲並降低相量估計的準確性，可能導致保護和控制機制發生故障或操作不當。保護繼電器在隔離故障部分和確保系統穩定性方面發揮著至關重要的作用，並依賴準確的訊號處理。DDC不僅影響波形，還會引入容易出錯的情況，可能導致誤跳脫或延遲故障清除，對系統的可靠性和安全性帶來嚴重風險。廣泛用於相量估計的基於傳統離散傅立葉變換(DFT) 的演算法特別容易受到故障電流中DDC 的影響。雖然DFT 在理想條件下有效，但當遇到衰減分量和諧波時，尤其是取樣率較低時，其效能會顯著惡化。低取樣率會加劇基於DFT 的估計值的不準確性，使其在瞬態快速變化和DDC 存在的情況下變得不可靠。這種限制直接影響了繼電器保護對故障快速、準確反應的能力，損害了故障分析的整體效果。因此，迫切需要能夠有效減輕DDC 影響並提高相量估計精度的先進技術，特別是在採樣率低和瞬態幹擾嚴重的環境中。
為了應對這些挑戰，所提出的多重延遲訊號消除（MDSC）濾波器已成為一種有前景的解決方案，為增強相量估計提供了創新方法。透過利用MDSC 濾波器，我們開發了三種先進方法來衰減DDC 分量，並能夠精確、快速地提取相量資訊。這些方法不僅提高了基頻相量估計的準確性，而且還證明了在受諧波、雜訊和非標稱頻率影響的條件下的穩健性。理論分析強調了這些基於MDSC 的方法的獨特優勢，包括它們以更高的取樣率有效執行的能力，從而克服了傳統DFT 方法面臨的限制。數值和模擬測試驗證了基於MDSC 的方法的優越性能，展示了它們在具有挑戰性的條件下準確估計相量的能力，為電力系統保護中更可靠、更高效的數位繼電器應用鋪平了道路。
這項關於衰減直流（DDC）估計的研究工作的成果如下：1）使用MDSC濾
波器的高頻調變技術：開發了一種先進的高頻調變技術，利用多重延遲訊號

消除（MDSC）濾波器進行精確估計衰減直流(DDC) 分量。2）利用MDSC濾波器進行下採樣高頻調變：提出了一種與高頻調變技術結合的下採樣方法，利用MDSC濾波器來提高計算效率，同時維持DDC估計的高精度。3）使用MDSC濾波器的基於四個半週期的演算法：設計了使用MDSC濾波器的基於四個半週期的演算法，能夠精確分割並改進對不同時間間隔內的DDC分量的分析。4) 採用MDSC 濾波器的新型下採樣DFT 方法：引入了一種使用源自MDSC濾波器的下採樣離散傅立葉變換(DFT) 方法進行DDC 估計的新方法，提高了計算衰減DC 分量的精度和魯棒性。這些貢獻共同提供了一個強大的框架，可以在各種實際應用中有效、準確地估計衰減直流分量。

Decaying DC offset (DDC) presents a significant challenge in power systems, particularly under fault conditions, where it introduces substantial distortion in the fault current waveform. This distortion complicates the reliable extraction of critical parameters, such as the magnitude and phase angle of the fundamental frequency component, which are essential for the precise operation of protective relays. The presence of DDC can delay and degrade the accuracy of phasor esti- mation, potentially leading to the malfunction or improper operation of protective and control mechanisms. Protective relays, which play a crucial role in isolating faulty sections and ensuring system stability, rely on accurate signal processing. DDC not only impacts the waveform but also introduces error-prone scenarios that may result in false trips or delayed fault clearance, posing serious risks to the system’s reliability and safety.
Traditional Discrete Fourier Transform (DFT)-based algorithms, widely used in phasor estimation, are particularly vulnerable to the effects of DDC in fault cur- rents. While DFT is effective under ideal conditions, its performance deteriorates significantly when confronted with decaying components and harmonics, especially when the sampling rate is low. Low sampling rates exacerbate the inaccuracies of DFT-based estimations, making them unreliable in scenarios with rapid tran- sient changes and DDC presence. This limitation directly impacts the ability of protective relays to respond promptly and accurately to faults, undermining the overall efficacy of fault analysis. Consequently, there is a critical need for advanced techniques that can effectively mitigate DDC effects and improve phasor estima- tion accuracy, particularly in environments with low sampling rates and significant transient disturbances.
To address these challenges, the proposed Multiple Delayed Signal Cancellation

(MDSC) filter has emerged as a promising solution, offering innovative methods for enhanced phasor estimation. By leveraging the MDSC filter, three advanced approaches have been developed to attenuate DDC components and enable pre- cise and rapid extraction of phasor information. These methods not only enhance the accuracy of fundamental frequency phasor estimation but also demonstrate robustness in conditions afflicted by harmonics, noise, and off-nominal frequen- cies. Theoretical analyses highlight the unique strengths of these MDSC-based methods, including their ability to perform effectively with higher sampling rates, thereby overcoming limitations faced by traditional DFT approaches. Numerical and simulation tests validate the superior performance of MDSC-based methods, showcasing their ability to accurately estimate phasors under challenging condi- tions, paving the way for more reliable and efficient digital relaying applications in power system protection.
The accomplishments of this research work on Decaying DC (DDC) estima- tion are as follows: 1) High-Frequency Modulation Technique using MDSC Filter: Developed an advanced high-frequency modulation technique that leverages the Multiple Delayed Signal Cancellation (MDSC) filter for accurate estimation of the Decaying DC (DDC) component. 2) Down-Sampling High-Frequency Modula- tion with MDSC Filter: Proposed a down-sampling methodology integrated with the high-frequency modulation technique, utilizing the MDSC filter to enhance computational efficiency while maintaining high accuracy in DDC estimation. 3) Four Half-Cycle-Based Algorithm using MDSC Filter: Designed a four-half-cycle- based algorithm employing the MDSC filter, enabling precise segmentation and improved analysis of the DDC component over distinct time intervals. 4) Novel Down-Sampling DFT Method with MDSC Filter: Introduced a new approach for DDC estimation using a Down-Sampling Discrete Fourier Transform (DFT) method derived from the MDSC filter, achieving enhanced precision and robust-

ness in calculating the Decaying DC component. These contributions collectively provide a robust framework for efficient and accurate estimation of the Decaying DC component in various practical applications.

Contents


Abstract (Chinese)    I

Abstract    III
Contents    VI
List of Figures    IX
List of Tables    XI
  Introduction    1
1    Background and Motivation    1
2    Phasor Estimation Techniques used in Digital Relays for Decaying
DC Removal    4
3    High-Frequency Modulation Technique using MDSC Filter    6
4    Down Sampling High-Frequency Modulation Technique using MDSC Filter    7
5    Four Half-Cycle Based Algorithm using MDSC Filter    8
  Phasor Estimation Techniques used in Digital Relays for Decaying DC Removal    10
1    Power System Protection    10
2    Digital and Numerical Relays    11
3    Phasor Estimation Methods    17
3.1    Introduction    17
3.2    Conventional DFT Method    20
3.3    Cosine Filter    22
3.4    Mimic Filter    23
3.5    Least-Square Methods    24
3.6    ANN    26
4    Multiple Delayed Signal Cancellation Method used for DDC Esti- mation    28
4.1    Single Phase MDSC Operator in Continuous-time    29
4.2    Single Phase MDSC Operator in Discrete-time    30
4.3    Recursive Realizations of MDSC Operators for Phasor Ex- tractions    32
5    Summary    38
  DDC Estimation Techniques using MDSC Filter    39
1    High-Frequency Modulation Technique using MDSC Filter (Pro- posed Method (a))    39
1.1    Introduction    39
1.2    DDC Estimation    40
1.3    Flowchart of the High-frequency Modulation Technique    44
2    Down-Sampling High-frequency modulation method using MDSC (Proposed Method (b))    45
2.1    Introduction    45
2.2    DDC Estimation    46
2.3    Flowchart of the High-frequency Modulation-based Down- Sampling Technique    49
3    Summary    50
  Four Half Cycle based Algorithm using MDSC Filter (Proposed Method (c)) :    51
1    Introduction    51
2    DDC Estimation    52
3    Flowchart of the Half Cycle based MDSC.    56
4    Performance Evaluation and Discussions    57
4.1    Computer Generated Signals    57
4.2    Basic Signal with Single DDC    58
4.3    Basic Signal with Two DDC    60
4.4    Basic Signal with Two DDCs and Harmonics    62
4.5    Basic Signal with Two DDCs and Harmonics and Noises    64
4.6    Basic Signal for Off-nominal Frequency    66
5    Real Transmission Line Simulation Studies    67
5.1    IEEE 9-Bus Power System    68
5.2    Test Case for Single Phase to Ground Fault    69
5.3    Test Case for Three Phase to Ground Fault    70
5.4    Summary    73
  Conclusion    76
Bibliography    80



List of Figures


1    Block diagram of basic numerical relays    13
2    Basic circuit for fault analysis    19
3    Fundamental component with DDC and harmonics    20
4    Magnitude of a fault current signal with/without DDC component.    22
5    Mimic circuit representation for eliminating DDC from the original
fault signal.    24
6    Block diagram basic ANN method.    27
7    Block diagram of MDSC: Direct form.    32
8    Block diagram of MDSC: Recursive form.    33
9    Bode plot for cMDSC when m=14    36
10    Bode plot for sMDSC when m=14.    36
11    Bode plot for cMDSC when m=16.    37
12    Bode plot for sMDSC when m=16.    37

1    Flowchart of the proposed method (a): High-frequency modulation.    45
2    Flowchart of the proposed method (b): High-frequency modulation based down-sampling.    50
1    Flowchart of the proposed method (c): Half cycle based MDSC.    56
2    Test case with 0.5 time constant: One DDC.    58
3    Test case with 5 time constant: One DDC.    59

4    Test case with 0.5 time constant: Two DDCs.    61
5    Test case with 5 time constant: Two DDCs.    62
6    Test case with 0.5 time constant: Two DDCs with harmonics.    63
7    Test cases with 5 time constant: Two DDCs with harmonics.    64
8    Test case with 0.5 time constant: Two DDCs with harmonics and
noise (40db).    65
9    Test case with 0.5 time constant: Two DDCs with harmonics and
noise (50db).    66
10    Test cases with 0.5 time constant: Off nominal frequency    67
11    IEEE 9 bus system.    68
12    Test case for IEEE 9-Bus System: LG fault with 0 (ohms).    69
13    Test case for IEEE 9-Bus System: LG fault with 5 (ohms).    70
14    Test case for IEEE 9-Bus System: LG fault with 5 (ohms) zoomed portion.    70
15    Test case for IEEE 9-Bus System: LLLG fault with 0 (ohms).    71
16    Test case for IEEE 9-Bus System: LLLG fault with 5 (ohms).    72
17    Test case for IEEE 9-Bus System: LLLG fault with 5 (ohms) zoomed portion.    72



List of Tables


1    Simulation Parameters.    28

1    Result comparison of 0.5 time constant- One DDC.    59
2    Result comparison of 5 time constant- One DDC.    59
3    Result comparison of 0.5 time constant- Two DDCs.    61
4    Result comparison of 5 time constant- Two DDCs    61
5    Result comparison of 0.5 time constant: Two DDC with harmonics    63
6    Result comparison of 5 time constant: Two DDC with harmonics.    63
7    Result comparison of 0.5 time constant: Two DDC with harmonics
and noise (40db).    65
8    Result comparison of 0.5 time constant: Two DDC with harmonics
and noise (50db).    65
9    Off nominal frequency condition.    67
10    Comparison result: LG fault with 0 (ohms).    69
11    Comparison result: LG fault with 5 (ohms).    71

                                

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