一個使用每週期二位元與數位斜坡轉換之十二位元兩百百萬頻率時序交錯之混合式連續漸進逼近式類比數位轉換器

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研究生：	酈又新 Lih, Yu-Hsin
論文名稱：	一個使用每週期二位元與數位斜坡轉換之十二位元兩百百萬頻率時序交錯之混合式連續漸進逼近式類比數位轉換器 A 12bit 200MS/s Time-interleaved Hybrid-SAR ADC with Two-bit-per-cycle and Digital-slope Conversions
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	黃柏鈞 Huang, Po-Chiun 鄭桂忠 Tang, Kea-Tiong 謝秉璇 Hsieh, Ping-Hsuan
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	59
中文關鍵詞：	類比數位轉換器、循序漸進逼近式、數位斜坡
外文關鍵詞：	ADC, SAR, Digital-slope
相關次數：	點閱：3 下載：0
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本論文提出一個使用四十奈米製程，操作於兩百百萬頻率的十二位元類比數位轉換器，以雙通道的時序交錯混合式每週期雙位元連續漸進逼近與數位斜坡技巧實現。
傳統循序漸進逼近式類比數位轉換器會因比較時間與電容穩定時間等原因使其操作速度較慢，本論文採用時序交錯架構與雙位元產出手法來加快操作速度，而時序交錯架構中的雙通道架構完全相同，並輪流交替進行收斂行為；雙位元產出則使用一雙通道共用的參考電壓數位類比轉換器與額外兩個離散時間比較器來達成。
而為了解決一般循續漸近式類比數位轉換器在高解析度規格下，電容切換所需能耗與離散時間比較器能耗的問題，本架構採用直接切換手法與兩階段式操作。直接切換手法能減少切換之電容，降低其切換能耗。而兩段式架構操作中第一階段使用在低解析度規格下擁有較佳能源效率的循續漸近式類比數位轉換器並搭配雙位元產出，經過冗餘位元位移後進行第二階段收斂，第二階段採用交互骨牌數位斜坡手法以連續時間比較器代替離散時間比較器降低能源消耗，並採用時域內差手法增加額外的一位元以壓低量化雜訊，達到較好的有效位元數。
藉由以上手法，使本架構能在較少的能耗下達到兩百百萬頻率的中間偏高速操作頻率，並能達到11位元以上的有效位元，並可應用在高速通訊系統中。

This thesis presents a hybrid ADC constructed with two-channel time-interleaved structure, with each channel composed by subrange SAR-based two-bit-per-cycle coarse and alternate-domino digital-slope fine, contribute resolution at 12-bit and operation frequency at 200MHz by TSMC 40nm process.
Conventional SAR ADC has a limit operation frequency due to the comparison time and DAC settling time. To solve this problem, the proposed ADC is composed by time-interleaved structure with two-bit-per-cycle method. The both channel are identically, it works alternatively with the sample clock in 50% duty cycle. The two-bit-per-cycle uses an extra two channel co-use reference DAC and two extra discrete-time comparator to contribute the function.
The another problem of conventional SAR is that the switching energy increases exponentially with the resolution, also, the discrete-time comparator costs dramatic energy to suppress the noise at the high resolution. To solve these problem, the direct-switching and subrange structure is used. The direct-switching can switch lease capacitance to reduce the switching energy. The subrange structure is constructed by SAR-based two-bit-per-cycle coarse and alternate-domino digital slope fine with the redundancy between coarse and fine. The SAR-base two-bit-per-cycle has well power efficiency in low resolution, and the continuous-time comparator of the digital slope has better power efficiency than the discrete-time comparator in high resolution with short operation time. Furthermore, a time-domain interpolation bit is insert into the fine ADC to suppress the quantization noise, make the ENOB better.
The method and structure mentioned below contribute the 11-bit ENOB 200MHz operation frequency ADC with low power, which can applicate in high speed communication system.

ABSTRACT    II
致謝    IV
CONTENTS    VI
LIST OF FIGURES    X
LIST OF TABLES    XIII
CHAPTER 1    INTRODUCTION    1
1    MOTIVATION    1
3    PERFORMANCE METRICS OF ADC    3
3.1    Nyquist Criterion    3
3.2    Nyquist Criterion    4
3.3    Quantization error    4
3.4    Offset and Gain Error    6
3.5    Differential Nonlinearity    7
3.6    Integral Nonlinearity    8
3.7    Signal-to-Noise Ratio    9
3.8    Effective Number of Bit (ENOB)    9
3.9    Figure of Merit    9
4    TARGET SPECIFICATION    10
5    THESIS ORGANIZATION    11
CHAPTER 2    SUCCESSIVE APPROXIMATION REGISTER ADC OVERVIEW    12
1    INTRODUCTION    12
2    OPERATION PROCEDURE OF CONVENTIONAL SAR ADC    13
3    CONSIDERATIONS OF SAMPLE AND HOLD    14
3.1    Turn-on Resistance    14
3.2    Charge Injection    15
3.3    Clock Feedthrough    15
3.4    KT/C Noise    16
4    CONSIDERATIONS OF CAPACITIVE DAC    17
4.1    DAC Parasitic Capacitance    18
4.2    DAC Capacitor Mismatch    18
4.3    Settling Time    18
5    CONSIDERATIONS OF COMPARATOR    19
5.1    Input Offset    20
5.2    Kickback Noise    20
6    SAR CONTROL LOGIC    21
7    SUMMARY    22
CHAPTER 3    CIRCUIT DESIGN CONSIDERATIONS    24
1    THE BOTTLENECKS OF SAR ADC    24
1.1    Operation Speed    24
1.2    Power Consumption in High Resolution    24
2    SOLUTION OF THE BOTTLENECKS    25
2.1    Solution to Enhance Operation Speed    25
2.2    Solution to suppress switching power consumption    26
2.3    Solution to suppress the comparator power consumption    26
3    PROPOSED TWO-BIT-PER-CYCLE COARSE ADC    27
3.1    Mechanism of Proposed Two-bit-per-cycle Method    27
3.2    Direct Switching Method    29
3.3    Non-ideal Effect and Residue Range    30
4    PROPOSED ALTERNATE-DOMINO DIGITAL SLOPE    31
4.1    Digital Slope    31
4.2    Alternate-domino Switching    32
4.3    Time Domain Interpolation    33
5    REDUNDANCY AND CALIBRATION    33
6    PROPOSED ADC    35
7    SUMMARY    36
CHAPTER 4    CIRCUIT IMPLEMENTATION    37
1    ARCHITECTURE OF PROPOSED ADC    37
2    DESIGN OF SAMPLE AND HOLD    38
3    DESIGN OF CAPACITIVE DAC    39
4    DESIGN OF DISCRETE-TIME COMPARATOR    40
4.1    Calibration    41
5    DESIGN OF DIRECT SWITCHING LOGIC    41
6    DESIGN OF CONTINUOUS-TIME COMPARATOR    42
6.1    Calibration    43
7    DESIGN OF ALTERNATE-DOMINO SWITCHING LOGIC    44
8    DESIGN OF REDUNDANT SHIFT LOGIC    45
9    DESIGN OF ENCODER    46
10    SUMMARY    47
CHAPTER 5    SIMULATION RESULTS    48
1    PRE-LAYOUT SIMULATION    48
2    POST-LAYOUT SIMULATION    50
3    NON-IDEAL EFFECTS    52
3.1    Increase of Power Consumption    52
3.2    Switching Timing Offset    52
3.3    D Flip-flop Latching Offset    53
4    MATLAB MODEL SIMULATION    54
5    PERFORMANCE SUMMARY AND COMPARISON    55
6    SUMMARY    56
CHAPTER 6    CONCLUSION AND FUTURE WORK    57
1    CONCLUSION    57
2    FUTURE WORK    57
BIBLIOGRAPHY    58


                                

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