簡易檢索 / 詳目顯示

回結果列表
研究生： 江孝友
Chiang, Hsiao-Yu
論文名稱： 迴路鎖:基於邏輯優化的迴路化邏輯加密技術
LOOPLock : LOgic OPtimization based Cyclic Logic Locking
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 黃俊達
Huang, Juinn-Dar
陳勇志
Chen, Yung-Chih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 27
中文關鍵詞： 硬體安全 、迴路化邏輯加密技術 、布林攻擊技術 、迴路化布林攻擊技術 、邏輯優化
外文關鍵詞： hardware security, cyclic logic locking, SAT Attack, CycSAT, logic optimization
相關次數： 點閱：2  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • SAT Attack，CycSAT和Removal Attack已經證明了它們能夠破解大多數現有的邏輯加密技術。在本文中，我們提出了一種新的迴路化邏輯加密技術來同時使這些攻擊技術無效。我們的主要目的是建構非組合性迴路來加密電路，並且在提供正確密碼時能夠保留這些非組合性迴路。實驗結果展示了該方法的有效性和低面積成本。

    SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities tobreak most existing logic locking methods. In this paper, we propose a new cycliclogic locking method to invalidate these attacks simultaneously. Our main intentionis to create non-combinational cycles to lock a circuit, and the cycles need to bepreserved when the secret key is fed. The experimental results show the effectivenessand low area overhead of the proposed method.

    中文摘要--------------i Abstract-------------ii 誌謝辭---------------iii Contents-------------iv List of Tables-------vi List of Figures------vii 1 Introduction--------1 2 Preliminaries-------4 2.1 Background--------4 2.2 Node Merging (NM)---5 2.3 NM-based cycle generation---7 3 Our Method--------------------10 4 Evaluation--------------------14 4.1 SAT Attack------------------14 4.2 CycSAT----------------------16 4.3 Removal Attack--------------18 5 Experimental Results----------19 6 Conclusions-------------------25 Bibliography--------------------26

    [1] Kimia Zamiri Azar et al., “SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks,” IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019, pp.
    97-122.
    [2] J.-H. Chen et al., “Synthesis and Verification of Cyclic Combinational Circuits,” in Proc. of SOCC, 2015, pp. 257-262.
    [3] Y.-C. Chen and C.-Y. Wang, “Fast Node Merging with Don’t Cares Using Logic Implications,” IEEE TCAD, pp. 1827-1832, 2010.
    [4] A. Chakraborty et al., “TimingSAT: Timing Profile Embedded SAT Attack,” in Proc. of ICCAD, 2018, pp. 6:1-6:6.
    [5] M. Chen et al., “Hardware Protection via Logic Locking Test Points,” IEEE TCAD, pp. 3020-3030, 2018.
    [6] J. A. Roy et al., “Ending Piracy of Integrated Circuits,” Computer, vol. 43, no. 10, pp. 30-38, 2010.
    [7] A. Rezaei et al., “Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks,” in Proc. of DATE, 2018, pp. 85-90.
    [8] S. Roshanisefat et al., “SRClock: SAT-resistant Cyclic Logic Locking for Protecting the Hardware,” in Proc. of GLSVLSI, 2018, pp. 153-158.
    [9] A. Sengupta and M. Rathor, “Security of Functionally Obfuscated DSP Core
    Against Removal Attack Using SHA-512 Based Key Encryption Hardware,”
    IEEE Access, vol.7, pp. 4598-4610.
    [10] K. Shamsi et al., “Cyclic Obfuscation for Creating SAT-Unresolvable Circuits,” in Proc. of GLSVLSI, 2017, pp. 173-178.
    [11] K. Shamsi et al., “AppSAT: Approximately deobfuscating integrated circuits,” in Proc. of HOST, 2017, pp. 95-100.
    [12] P. Subramanyan et al., “Evaluating the Security of Logic Encryption Algorithms,” in Proc. of HOST, 2015, pp. 137-143.
    [13] Y. Xie and A. Srivastava, “Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction,” In Proc. of DAC, 2017, pp. 1-6.
    [14] Y. Xie and A. Srivastava, “Mitigating SAT Attack on Logic Locking,” in Proc. of International Conference on Cryptographic Hardware and Embedded Systems, 2016, pp. 127-146.
    [15] M. Yasin et al., “SARlock: SAT Attack Resistant Logic Locking,” in Proc. of
    Host, 2016, pp. 236-241.
    [16] M. Yasin et al., “Provably-Secure Logic Locking: From Theory To Practice,” in Proc. ACM Conf. on Computer Communications Security, 2017, pp. 1601-1618.
    [17] M. Yasin et al., “Removal Attacks on Logic Locking and Camouflaging Techniques,” IEEE Trans. on Emerging Topics in Computing, to be published, doi: 10.1109/TETC.2017.2740364.
    [18] M. Yasin et al., “Security Analysis of Anti-SAT,” in Proc. of ASPDAC, 2016, pp. 342-347.
    [19] G. Zhang et al., “TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing,” in Proc. of DATE, 2018, pp. 91-96.
    [20] H. Zhou et al., “CycSAT: SAT-based attack on cyclic logic encryptions,” in
    Proc. of ICCAD, 2017, pp. 49-56.
    [21] IWLS2005 Benchmarks. [Online]. Available:
    http://iwls.org/iwls2005/benchmarks.html

    QR CODE