隨著進入大數據與人工智慧世代，電子產品的需求越趨重要，其中數據儲存裝置更是值得被重視，記憶裝置除了需要提供足夠記憶容量，其高效率運算與低功耗也是未來追求的目標。以鐵電材料為基礎開發的新穎鐵電記憶體，不僅具有傳統非揮發性記憶體的特性，其低功耗與高速操作又相容於現有CMOS製程，這些特性使鐵電記憶體被推崇為下世代的記憶體。
本論文著重於利用介面工程方式改善鐵電電容元件的特性，其中包含提升鐵電穿隧元件的穿隧電阻值，與改善鐵電電容的喚醒、鐵電疇去釘扎和子循環下的特性，甚至提升鐵電電容的耐久度與降低操作電壓等。首先，以較薄的鐵電層搭配高介電常數氮氧化鋁，與使用較低功函數鋁化鈦金屬使鐵電穿隧元件特性得到改善，由於鋁化鈦使勢壘高度下降約1電子伏特，使低阻態時的電流密度上升，進而讓穿隧電阻值得到提升，鋁化鈦鐵電穿隧元件表現出較高的穿隧電阻值30，且經過106耐久度測試，穿隧電阻值仍然可以維持30，而沒有劣化。另一方面，高介電常數氮氧化鋁使操作分壓更容易落在鐵電層上，進而擁有較低的操作電壓約5伏特，並且保有較高的操作速度約500奈秒。接著，為了改善鐵電層喚醒的負面效應，本論文引入二氧化鋯作為種子層與應力層使鐵電電容特性得到大幅提升，在擁有雙層鐵電層與雙層二氧化鋯的結構下，其表現出無喚醒的特性，並且提高了正交晶向的比例使其在初始時即擁有相當大的極化值37 µC/cm2，不僅如此，此結構也首次展示了鐵電元件可以達成四位元操作的能耐，並且可重複操作至107次而沒有崩潰。緊接著，為了提升鐵電電容對於耐久度次數與操作電壓的考量，本論文分別使用了原子層沉積改善介面的製程方式來完成。其中，利用氮化鉭可以提高有效功函數的方式，將其穿插於鐵電層與上下電極之間，藉此提升元件對於電壓的耐受度，並且提升崩潰電壓，使擁有氮化鉭的鐵電電容可以在常數電壓3.55 V連續操作下維持約略10-100秒，並使元件的耐久度次數大幅的提升至3×1010次。此外，使用連續製程沉積的方式，也降低了鐵電層中的氧空缺，透過XPS得知非晶格氧比例約略只有16.7 %，而傳統物理氣相沉積的製程方式則高達29.8 %。另一方面，為了降低元件的操作電壓，論文中使用了非晶氮化鈦穿插於鐵電層間，由於非晶的特性使正交晶向的介面能小於單斜晶向與四方晶向的介面能，使鐵電電容擁有較高的正交晶向比例，進而改善鐵電電容的特性，其中包括在2 V較低的操作電壓即可將鐵電疇完全翻轉。論文中也採用了回春操作模式搭配三位元操作，使元件在連續操作後，發生疲乏時，透過此方法可以回歸初始儲存狀態，使元件的三位元操作的耐久度次數達到3×107次。

As we enter the era of big data and artificial intelligence, the demand for electronic products becomes increasingly important. Among them, data storage devices are particularly worthy of attention. Memory devices not only need to provide sufficient storage capacity but also aim for high-efficiency computing and low power consumption in the future. Novel ferroelectric memories developed based on ferroelectric materials not only possess characteristics of traditional non-volatile memories but also offer low power consumption and high-speed operation compatible with existing CMOS processes. These features make ferroelectric memory highly regarded as the memory of the next generation.
This thesis focuses on improving the characteristics of ferroelectric capacitor devices through interface engineering. This includes enhancing the tunneling electro-resistance ratio of ferroelectric tunneling junction and improving the characteristics of wake-up, ferroelectric domain depinning, and sub-cycling of ferroelectric capacitors, as well as enhancing endurance and reducing operating voltage. Initially, thinner ferroelectric layers are paired with high dielectric constant AlON, along with the use of lower work function TiAl, to improve the characteristics of ferroelectric tunneling junction. Due to TiAl lowering the barrier height by approximately 1 eV, the current density in the low resistance state increases, which consequently enhances the tunneling electro-resistance (TER). The TiAl ferroelectric tunneling device demonstrates a high TER value of 30. Furthermore, after 106 endurance cycles, the TER remains at 30 without degradation. On the other hand, the high dielectric constant of AlON makes it easier for the operating voltage to fall across the ferroelectric layer, resulting in a lower operating voltage of about 5 V and maintaining a high operating speed of approximately 500 ns. Furthermore, to mitigate the negative effects of wake-up in the ferroelectric layer, this thesis introduces ZrO¬2 as a seed and stress layer to significantly enhance the characteristics of ferroelectric capacitors. With the structure featuring double ferroelectric layers and double ZrO2, it exhibits wake-up-free characteristics and increases the proportion of orthogonal crystal orientations, resulting in a significantly larger remanent polarization value of 37 µC/cm2 in its pristine state. Moreover, this structure also demonstrates, for the first time, the capability of ferroelectric devices to achieve quadruple-level operations, and it can be repeatedly operated up to 107 times without breakdown. Following that, in order to enhance the considerations of endurance cycles and operating voltage for ferroelectric capacitors, this thesis employs atomic layer deposition to improve interface processes. Specifically, by utilizing TaN to increase the effective work function, it is interleaved between the ferroelectric layer and the upper and lower electrodes. This enhances the device's tolerance to voltage and increases the breakdown voltage. The ferroelectric capacitor with TaN can maintain continuous operation at a constant voltage of 3.55 V for approximately 10-100 seconds, thereby significantly increasing the device's endurance to 3×1010 cycles. Furthermore, employing a continuous deposition process also reduces oxygen vacancies within the ferroelectric layer. Through XPS, it is determined that the proportion of non-lattice oxygen is approximately 16.7%, In contrast, the conventional physical vapor deposition process has a proportion as high as 29.8%. On the other hand, to decrease the operating voltage of the device, the thesis utilizes amorphous TiN interleaved within the ferroelectric layers. The amorphous nature of TiN results in lower interfacial energy for the orthogonal crystal orientation compared to the monoclinic and tetragonal orientations, thereby increasing the proportion of orthogonal crystal orientations in the ferroelectric capacitor and improving its characteristics, including the complete reversal of ferroelectric domains at a relatively low operating voltage of 2 V. The thesis also incorporates a rejuvenation operation mode combined with triple-level cell operations, allowing the device to return to its initial stored state when fatigue occurs after continuous operations. This method significantly increases triple-level cell operation times up to 3×107.

Chapter 1
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Chapter 2
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Chapter 3
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Chapter 4
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Chapter 5
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