簡易檢索 / 詳目顯示

研究生: 游昭霖
Chao-Lin Yu
論文名稱: CR Switch: A Load-Balanced Switch with Contention and Reservation
指導教授: 張正尚
Cheng-Shang Chang
口試委員:
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 通訊工程研究所
Communications Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 112
中文關鍵詞: 負載平衡競爭保留封包順序封包交換率延遲效能
外文關鍵詞: load-balancing, contention, reservation, packet order, throughput, average delay
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 負載平衡交換機近來在交換機的研究上獲得很大的關注。這是因為他們比現有文獻中的交換機架構更具擴充性。然而,因為每個封包流都具有多重路徑以通過此負載平衡交換機,在這樣的負載平衡式交換機裡的封包流很可能會產生封包順序錯亂的問題。在[23]裡由史丹佛大學所提出的UFS方案以及在[10]裡由我們研究團隊先前所提出的信箱交換機是針對這樣的封包失序問題的可擴充性的解決方案。雖然UFS方案可以逹到百分百交換率[23],封包延遲卻相當大(即使是在低交通流量)。這在研究的認知上被稱為挨餓問題。而另一方面,研究顯示信箱交換機(當δ為零)只能達到百分之五十八的交換率[10]。但是,信箱交換機的優點是在低交通流量時,封包所面臨的延遲相當小。

    我們的第一項研究貢獻在於找出信箱交換機的交換率。我們發現信箱交換機的兩種極端,也就是δ=0 以及δ=∞,產生兩種不同的交換率限制。當δ=0 時,我們研究以時框為基礎的信箱交換機之交換率。我們發現當時框大小F 趨近∞時,交換率以1/√F的速率趨近於1。而當δ=∞時,此信箱交換機的最大穩定交換率為0.6748。一個有趣的現象是,當此信箱交換機進入非穩態時,其交換率隨著交通流量遞增。並且在交通流量為1.0時達到最大的非穩態交換率為0.6786。

    我們的整體研究工作最主要的貢獻在於提出了一個交換機架構,我們稱之為競保交換機。此交換機可以同時擁有在[23]裡的UFS方案之優點與在[10]裡的δ為零的信箱交換機之優點。我們的研究顯示此競保交換機可達到百分百之交換率,以及可以將封包依序傳送(就如同UFS方案)。然而,我們也可以同時在低交通流量時維持相當低的封包遲延(就如同δ為零的信箱交換機)。這項研究的主要想法,就如同由Tobagi以及Kleinrock於[51]的先前領航工作對多重使用通道所提出的相法,是讓此競保交換機操作於兩種不同的模式:競爭模式(於低交通流量時)以及保留模式(於高交通流量時)。我們的方案跟[51]裡的系統最大的不同點在於我們的系統擁有多重平行通道,而在[51]裡卻只有一個。在這多重的競保(競爭與保留)通道裡最大的挑戰就在於維持封包的順序。使得我們進行這些操作與達成這些目的之關鍵創新在於一個新的暫存器管理方案。我們稱此暫存器管理方案為I-VOQ(可安插式虛擬輸出佇列)。在此I-VOQ技術下,我們對此競保交換機的兩個效能保證(百分百交換率與封包依序傳遞)提出嚴格的數學證明。依電腦模擬的結果,我們也展示此競保交換機的封包延遲特性:在低交通流量時此競保交換機的封包延遲幾乎與信箱交換機相同,並且與UFS方案相較之下顯得非常小。甚且,當被與填充時框方案[21]相比時(這是一個由伊利諾大學香檳分校所提出為了解決UFS方案裡挨餓問題的改善方案),我們的封包延遲效能於低交通流量時一樣也是好相當多並且在高交通流量時兩者相去不遠。


    Load-balanced switches have received a great deal of attention recently as they are much more scalable than other existing switch architectures in the literature. However, as there exist multiple paths for flows of packets to traverse through load-balanced switches, packets in such switches may be delivered out of order. The UFS scheme in [23] proposed by Stanford University and the mailbox switches in [10] proposed by our research team are scalable solutions to solve such an out-of-sequence problem. Though the UFS scheme is shown to achieve 100% throughput [23], the packet delay is large (even in light traffic). This is known as the starvation problem. On the other hand, the mailbox switch (with δ= 0 in [10]) was shown to have only 58% throughput. The advantage of the mailbox switch is its low packet delay in light traffic.

    Our first contribution is to find the throughput limitations in the mailbox switch. We found that there are two kinds of throughput limitations in the two extreme schemes of the mailbox switches, i.e., the δ=0 scheme and the δ=∞ scheme. In theδ=0 scheme, we study the throughput for the frame-based mailbox switches with frame size F. We find that the throughput goes to 1.0 in the order of 1/√F as F goes to ∞. On the other hand, in the δ=∞ scheme, we found that the maximum stable throughput is 0.6748. An interesting phenomenon is that the throughput keeps growing with the arrival rate when the arrival rate is greater than the maximum stable throughput. In particular, we show that the maximum unstable throughput is 0.6786 when the arrival rate reaches 1.0.

    The main contribution of our research is to propose a switch architecture, called the CR switch, that can have the advantages of both the UFS scheme in [23] and the mailbox switch withδ= 0 in [10]. We show that the CR switch achieves 100% throughput and delivers packets in order (as in the UFS scheme), while maintaining low packet delay in light traffic (as in the mailbox switch with δ= 0). The main idea, as pointed out in the pioneer work by Tobagi and Kleinrock [51] for a multiple access channel, is to have the CR switch operating in two modes: the contention mode (in light traffic) and the reservation mode (in heavy traffic). The difference between our scheme and [51] is that our system has multiple parallel channels while there is only one in [51]. The challenge in multiple CR (Contention and Reservation) channels is to maintain packets in sequence. The key innovation that enables us to do this is a new buffer management scheme, called I-VOQ (virtual output queue with insertion). With the I-VOQ technique, we give rigorous mathematical proofs for 100% throughput and in order packet delivery of the CR switch. By computer simulations, we also demonstrate that the average packet delay of the CR switch in light traffic is almost the same as that in the mailbox switch and it is considerably smaller than that in the UFS scheme. Moreover, when compared with the Padded Frame scheme [21], an improved scheme proposed by the University of Illinois at Urbana Champaign for the starvation problem in the UFS scheme, our delay performance is also much better in light traffic and comparable in heavy traffic.

    Contents i List of Figures iv 1 Introduction 1 1.1 Basic switch architectures 5 1.1.1 Output-buffered switches 5 1.1.2 Input-buffered switches 6 1.2 The load-balanced switches 11 1.3 Results and the organizations 14 2 Throughput limitations in the mailbox switches 17 2.1 The generic mailbox switches 18 2.2 The throughput limitations in the frame-based mailbox switch with δ = 0 24 2.2.1 The generalized head of line blocking problem in the frame-based mailbox switches with δ = 0 25 2.2.2 The generalized Pollaczek-Khinchin formula 31 2.2.3 An algorithm to solve the ‾xed point problem for throughput analysis 41 2.2.4 Bounds and approximations 44 2.2.5 Numerical Studies and Simulations 47 2.3 The throughput limitations in the mailbox switch with δ = ∞ 48 3 The CR Switches 54 3.1 The switch architectures 55 3.1.1 Symmetric TDM switches 56 3.1.2 I-VOQs 57 3.1.3 Contention mode and reservation mode 58 3.2 In order delivery 62 3.2.1 General properties of I-VOQs 62 3.2.2 The proof for the in-order-delivery 64 3.3 100% throughput 65 3.3.1 WC(K,D) queues 65 3.3.2 A memory bound for input buffers 68 3.3.3 A memory bound for central buffers 69 3.4 Simulation studies on the average delay 73 3.4.1 Average delay under the uniform i.i.d. traffic 74 3.4.2 Methods to advance the contention pointers 76 3.4.3 Compared to the padded frame scheme 80 3.4.4 Compared to the iSLIP and to the ideal output-buffered switch 83 3.5 Fairness issues in the average delay 87 3.5.1 The contention priorities due to the TDM connections 87 3.5.2 Re-mapping ports to balance the contention priorities 89 3.5.3 Blocking of service in the contention mode 89 4 Conclusions and Future Studies 93 4.1 Discussions 94 4.2 Future studies 99 A Proof for Lemma 10 100 B Proofs for the CR switch 103 B.1 Proof of Proposition 17 103 B.2 Proof of Lemma 26 104

    [1] M. Ali and H. Nguyen. A neural network implementation of an input access scheme in a high-speed packet switch. In Proc. GLOBECOM, pages 1192-1196, 1989.
    [2] T. Anderson, S. Owicki, J. Saxes, and C. Thacker. High speed switch scheduling for local area networks. ACM Transactions on Computer Systems, 11:319-352, 1993.
    [3] F. Baccelli and P. Br¶emaud. Elements of Queueing Theory. Berlin Heidelberg: Springer-Verlag, 2003.
    [4] G. Birkhoff. Tres observaciones sobre el algebra lineal. Univ. Nac. Tucum¶an Rev. Ser. A, 5:147-151, 1946.
    [5] G. Brassard and P. Bratley. Fundamentals of Algorithmics. New Jersey: Prentice Hall, 1996.
    [6] T. X. Brown and K. H. Liu. Neural network design of a banyan network controller. In IEEE J. Select. Areas Commun, volume 8, pages 1289{1298, October 1990.
    [7] C.-S. Chang. Performance Guarantees in Communication Networks. London: Springer-Verlag, 2000.
    [8] C.-S. Chang, D.-S. Lee, and Y.-S. Jou. Load balanced birkhoff-von neumann switches, part i: one-stage buffering. Computer Communications, 25:611-622, 2002.
    [9] C.-S. Chang, D.-S. Lee, and C.-M. Lien. Load balanced birkhoff-von neumann switch, part ii: Multi-stage buffering. Computer Communications, 25:623-634, 2002.
    [10] C.-S. Chang, D.-S. Lee, Y.-J. Shih, and C.-L. Yu. Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets. IEEE Trans. on
    Communications, 56:136-149, 2008.
    [11] C.-S. Chang, D.-S. Lee, and C.-L. Yu. Generalization of the pollaczek-khinchin formula for throughput analysis of input-buffered switches. In IEEE INFOCOM, volume 2, pages 960-970, Miami, FL, April 2005.
    [12] C.-S. Chang, D.-S. Lee, and C.-Y. Yue. Providing guaranteed rate services in the load balanced birkhoff-von neumann switches. In Proceedings of IEEE INFOCOM, 2003.
    [13] H. J. Chao, J. Song, N. S. Artan, G. Hu, and S. Jiang. Byte-focal: a practical load balanced switch. In IEEE HPSR, May 2005.
    [14] S.-T. Chuang, A. Goel, N. McKeown, and B. Prabhakar. Matching output queueing with a combined input output queued switch. IEEE Journal on Selected Areas in
    Communications, 17:1030-1039, 1999.
    [15] J. Dai and B. Prabhakar. The throughput of data switches with and without speedup. In Proceedings of IEEE INFOCOM, pages 556{564, Tel Aviv, Isreal, March 2000.
    [16] W. Feller. An introduction to probability theory and its applications, volume 2. Wiley, New York, 2 edition, 1971.
    [17] H. N. Gabow and R. E. Tarjan. Faster scaling algorithms for network problems. SIAM J. Comput., 18:1013-1036, 1989.
    [18] D. Gross and C.M. Harris. Fundamentals of Queueing Theory. Wiley, New York, 3 edition, 1998.
    [19] J. J. Hopfield. Neural networks and physical systems with emergent collective computational abilities. In Proc. Natl. Acad. Sci., pages 2554-2558, April 1982.
    [20] C.-H. Huang, J.-S. Wang, and Y.-C. Huang. Design of high-performance cmos priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. IEEE Journal of Solid-State Circuits, 37(1):1030-1039, January 2002.
    [21] J.-J. Jaramillo, F. Milan, and R. Srikant. Padded frames: a novel algorithm for stable scheduling in load balanced switches. In Proceedings of IEEE CISS, Princeton, NJ, March 2006.
    [22] M. J. Karol, M. G. Hluchyj, and S. P. Morgan. Input versus output queueing on a space-division packet switch. IEEE Transactions on Communications, 35(12), December 1987.
    [23] I. Keslassy, S.-T. Chuang, K. Yu, D. Miller, M. Horowitz, O. Solgaard, and N. McKeown. Scaling internet routers using optics. In Proceedings of ACM SIGCOMM,
    Karlsruhe, Germany, August 2003.
    [24] I. Keslassy and N. McKeown. Maintaining packet order in two-stage switches. In Proceedings of IEEE INFOCOM, New York, 2002.
    [25] L. Kleinrock. Queueing Systems, Volume I: Theory. New York: Wiley & Sons, 1975.
    [26] C. Kolias and L. Kleinrock. Throughput analysis of multiple input queueing in atm switches. In Proc. Broadband Communications, pages 382-393, London, U.K, 1996.
    [27] P. R. Kumar and S. P. Meyn. Stability of queueing networks and scheduling policies. IEEE Transactions on Automatic Control, 40(2), Febuary 1995.
    [28] C. Kun, S. Quan, and A. Mason. A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. In Proceedings of IEEE ISCAS, volume 2, pages 753-
    756, May 2004.
    [29] W.E. Leland, M.S. Taqqu, W. Willinger, and D.V. Wilson. On the self-similar nature of ethernet tra±c. IEEE/ACM Transactions on Networking, 2:1-15, 1994.
    [30] E. Leonardi, M. Mellia, F. Neri, and M. A. Marsan. On the stability of input-queued switches with speed-up. IEEE transactions on Networking, 9(1), Febuary 2001.
    [31] Y.-W. Leung. Neural scheduling algorithms for time-multiplex switches. IEEE journal on selected areas in communications, 12(9), December 1994.
    [32] S.-Q. Li. Performance of trunk grouping in packet switch design. In IEEE INFOCOM, volume 2, pages 688{693, Bal Harbour, FL, April 1991.
    [33] S.-Y. R. Li. Algebraic Switching Theory and Broadband Applications. Academic Press, 2001.
    [34] Y. Li, S. Panwar, and H.-J. Chao. On the performance of a dual round-robin switch. In Proceedings of IEEE INFOCOM, pages 1688-1697, 2001.
    [35] Y. Li, Z. Tang, G.-P. Xia, and R.-L. Wang. A positivel self-feedbacked hopfield neural network architecture for crossbar switching. IEEE transactions on circuits and systems, 52(1), January 2005.
    [36] S. Liew and K. Lu. Performance analysis of asymmetric packet switch modules with channel grouping. In Proc. of IEEE INFOCOM, volume 2, pages 668-676, June 1990.
    [37] B. Lin and I. Keslassy. The concurrent matching switch architecture. In Proc. of IEEE INFOCOM, Barcelona, Spain, April 2006.
    [38] D. V. Lindley. The theory of queues with a single server. In Proc. Camb. Phil. Soc., volume 48, pages 277-289, 1952.
    [39] R. M. Loynes. The stability of a queue with non-independent inter-arrival and service times. In Proc. Camb. Phil. Soc., volume 58, pages 497-520, 1962.
    [40] N. McKeown. The iSLIP scheduling algorithm for input-queued switches. IEEE/ACM Transactions on Networking, 7:188-201, 1999.
    [41] N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand. Achieving 100% throughput in an input-queued switch. IEEE Transactions on Communications, 47(8):1260-1267, August 1999.
    [42] E. Oki, R. Rojas-Cessa, and H. J. Chao. A pipeline-based approach for maximal-sized matching scheduling in input-buffered switches. IEEE Commun. Letters, 5, June 2001.
    [43] A.K. Parekh and R.G. Gallager. A generalized processor sharing approach to flow control in integrated service networks: the single-node case. IEEE/ACM Transactions on Networking, 1:344-357, 1993.
    [44] A. Pattavina. Multichannel bandwidth allocation in a broadband packet switch. IEEE Journal on Selected Areas in Communications, 6(9), December 1988.
    [45] S. M. Ross. Stochastic Processes. New York: J. Wiley & Sons, 1983.
    [46] M. Schwartz. Broadband Integrated Networks. New Jersey: Prentice Hall, 1996.
    [47] D. Stoyan. Comparison Methods for Queues and Other Stochastic Models. Berlin:J. Wiley & Sons, 1983.
    [48] Y. Takefuji and K.-C. Lee. An artificial hystersis binary neuron: a model suppressing the oscillatory behaviours of neural dynamics. Biologic Cybern, 64:353-356, 1991.
    [49] Y. Tamir and H.-C. Chi. Symmetric crossbar arbiters for vlsi communication switches. IEEE Transactions on Parallel and Distributed Systems, 4:13-27, 1993.
    [50] G. Thomas. Bifurcated queueing for throughput enhancement in input queued switches. IEEE Communications Letter, 1:56-57, March 1997.
    [51] F. Tobagi and L. Kleinrock. Packet switching in radio channels: Part III polling and (dynamic) split-channel reservation multiple access. IEEE Transactions on
    Communications, 24(8):832-844, August 1976.
    [52] T. P. Troudet and S. M. Walters. Hopfield neural network architecture for crossbar switch control. IEEE Trans. Circuits Syst., 38:42-57, January 1991.
    [53] C.-Y. Tu, C.-S. Chang, D.-S. Lee, and C.-T. Chiu. Design a simple and high performance switch using a two stage switch architecture. In Proceedings of IEEE
    Globecom, 2005.
    [54] J. Turner. Strong performance guarantees for asynchronous crossbar schedulers. In Proceedings of IEEE INFOCOM, Barcelona, April 2006.
    [55] J. von Neumann. A certain zero-sum two-person game equivalent to the optimal assignment problem. In Contributions to the Theory of Games, volume 2, pages
    5-12, Princeton University Press, Princeton, New Jersey, 1953.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE