研究生: |
洪端佑 |
---|---|
論文名稱: |
晶片尺寸封裝電路板層級衝擊測試可靠度分析 Reliability Assessment of Chip Size Package under Board-level Drop Test |
指導教授: | 江國寧 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 動力機械工程學系 Department of Power Mechanical Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 142 |
中文關鍵詞: | 晶圓級晶片尺寸封裝 、應力緩衝層 、銅導線 、掉落試驗規範 、有限元素分析 、可靠度分析 |
相關次數: | 點閱:3 下載:0 |
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近年來消費性電子產品如行動電話、隨身硬碟、數位相機、個人數位助理等,多以小尺寸、輕量化與多功能為考量下陸續問世;然而,可攜性行動電子產品於使用過程中亦容易發生掉落情形,故針對增進行動電子產品可靠度與其內部封裝元件之動態行為探討所進行的相關研究即顯得日益重要。
本研究之主要目的為對於一具應力緩衝層之封裝結構進行電路板層級掉落試驗研究,於錫球下方之填充材料與介電層等高分子材料均為良好之應力緩衝材料,可有效釋放於撞擊過程中所產生之應力波,進而提升錫球之可靠度。由於錫球可靠度能藉由高分子材料優異之形變能力加以改善,故封裝結構之失效區域與傳統之晶圓級晶片尺寸封裝其結構失效區域有所不同;另,此高分子材料過大之變形可能導致於導線部分另一產品可靠度問題,並造成佈線層承受較大之應力波而產生破壞。
電子元件工業聯合會(Joint electron device engineering council, JEDEC)中之測試板(即印刷電路板)層級掉落試驗規範(Board-level drop test condition B)其相關規範適用於行動式電子產品之可靠度評估;於試驗中掉落台(Drop table)升高至所需要的高度後,以自由落體的方式讓掉落台沿著導桿自由落下,並產生一近似半正弦波之時間相關加速度函數,其最大加速度為1500G,脈衝波時間為0.5毫秒,並根據此規範進行實際掉落實驗。本研究於動態模擬部份使用有限元素分析軟體LS-DYNA®,並觀察測試板與封裝體於撞擊瞬間之機械行為,分為三個研究階段:第一階段,將實際量測所得之加速度與脈衝波時間輸入至有限元素模型,本模擬方法之可行性能藉由實際應變量之量測得到一定程度之驗證;第二階段,建立傳統之晶片尺寸封裝模型與具應力緩衝層之新型封裝模型,進行兩類型封裝之機械行為比較;第三階段,建立更細部之具銅導線之新型封裝模型。有別於其他掉落試驗研究,本研究主要針對具較佳錫球可靠度之新型封裝結構其銅導線部份之機械行為與力學趨勢進行探討。
研究結果可發現,具應力緩衝層之新型封裝結構於錫球可靠度部分已被有效的改善,然而,於導線部分產生另一產品可靠度問題;於改善銅導線可靠度部份,彎曲式之導線可有效降低導線頸部之應力集中現象,此外,較強之介電層亦可適度抑制導線過大之變形。本研究進行掉落測試動態模擬分析並與實驗結果進行相當之驗證,研究結果指出新型封裝設計可大幅提升晶片掉落測試之可靠度。
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