In this work, a lateral 4H-SiC two-zone RESURF MOSFET is demonstrated. Compared with the conventional RESURF structure, a two-zone structure improves design optimization for breakdown voltage and on-resistance without causing gate oxide breakdown. In addition, a top lightly doped epitaxial p-layer is used to increase the channel mobility and therefore decrease on-resistance. In device fabrication, a graphite cap is used to reduce surface roughness during implant anneal, and NO anneal is used to reduce oxide/SiC interface traps, which translates into better device performance.
The best achieved on-resistance is 31mΩcm2 for a device with 3μm channel length and 20μm drift region. As for the voltage blocking capability, the best achieved breakdown voltage is 3689V for a device with 5μm channel length and 160μm drift region. The BV is not as high as predicted by simulation. This might be due to the implant activation not being precisely controlled. The best achieved BFOM is 30.7MW/cm2, from a device with 3μm channel length and 20μm drift region. The breakdown voltage is 1254V, and the on-resistance is 63.6mΩcm2.

本論文為製作橫向高電壓4H碳化矽雙漂移區金氧半場效電晶體。比較起傳統RESURF結構，雙漂移區結構在設計崩潰電壓與導通電阻最佳化的同時，改善了閘極氧化層提早崩潰的情形。此外，在基板上磊晶了一層輕摻雜p-layer，用來提高通道遷移率，達到降低導通電阻值的目的。元件製程上，利用在摻雜活化時旋塗石墨層降低表面粗糙度以及一氧化氮回火的方式減少碳化矽與二氧化矽之間的表面缺陷，使其電性上有更好的表現。
量測結果得知，在通道長度3μm、漂移區長度20μm的元件中，其導通電阻最低達到31mΩcm2；崩潰特性方面，在通道長度5μm、漂移區長度160μm的元件中，其崩潰電壓最高達到3689V，但沒有當初模擬所預期來的高，推斷是活化率控制不佳所導致。以BFOM值來說，在通道長度3μm、漂移區長度20μm的元件，最佳值在崩潰電壓為1254V、導通電阻為51.2mΩcm2，其BFOM值為30.7MW/cm2。

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