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研究生: 鄭孝宏
Hsiao Hung Cheng
論文名稱: 架構於H.264立體視訊編碼之視差估測架構設計與分析
Design and Analysis of Disparity Prediction Architecture for H.264 based Stereo Video Coding
指導教授: 陳永昌
Yung Chang Chen
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 63
中文關鍵詞: 立體視訊視訊編碼視差架構
外文關鍵詞: Disparity, Video Coding, Architecture, H.264, Stereo Video
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  • 在本篇論文中,我們設計並實現了立體電視訊號壓縮的預測核心。初步以軟體建立整個motion-disparity混合估測系統,模擬並且改善演算法,提升估測精確度。最後再以Xilinx FPGA平台實現硬體架構,確保disparity估測核心的正確性與實際效能。

    □ 最基本的立體電視必須提供左右兩眼視訊以產生立體視覺效應,如此則需要兩個視訊channel,傳輸兩倍的資料量,壓縮核心的運算量也需要兩倍以上。比起單純的將兩個channel分別地使用H.264規格壓縮,使用motion-disparity混和預測的核心,可以再進一步的減少輔助channel估測的計算量。相較於單純的以H.264 variable block size的運動向量來估測輔助的channel,使用我們所提出的motion disparity 混合估測架構可以大幅地減少硬體複雜度70%以上並且保有一定的估測品質與立體視覺效應。

    □ 因為壓縮兩個channel的資料,需要兩份motion estimation的運算核心,但利用兩個channel之間的視差位移量(disparity vector)與運動位移量(motion vector)之間的關係,就可以只做單一channel的運動估測,在配合視差量,重建出另外一個channel的運動估測,如此一來就可以省下一個channel的運動估測運算量。在加上視差估測所需的硬體複雜度遠小於運動估測,所以整個硬體架構就可以比原來精簡許多,藉此達成減少硬體複雜度與低功率的目標。並且最後估測出來的仍是運動向量,可以直接使用傳統的H.264解碼器來重建出輔助channel的視訊畫面,不需額外設計相對應的硬體架構,如此可確保混合估測系統與一般系統的相容性,達到立體視訊系統普及化的目的。


    In this thesis, we propose a prediction scheme for stereo video with less computation complexity. The correspondence between disparity and motion vector is exploited and we can reduce the prediction complexity according to this relation. As the compatibility consideration with stereo video system, our prediction architecture is based on the H.264 standard. Simulation results show that the proposed coding algorithm can reduce huge computation complexity and maintain acceptable video quality and depth perception.

    It needs main and auxiliary images for stereo perception of human visual system, so double data transmission, computation complexity, and hardware resource are necessary for stereo video. Fortunately, we can utilize the relation of stereo image pair to reduce stereo video coding overhead. Because the computational complexity of disparity estimation is much less than motion estimation, the prediction architecture of auxiliary channel can be simplified enormously. Fewer hardware complexity and lower power consumption can be achieved using proposed motion and disparity hybrid prediction architecture.

    The motion vectors in the auxiliary channel acquired by the motion and disparity hybrid prediction can be used to reconstruct auxiliary frame directly. It means that we can use conventional H.264 decoder to decoder auxiliary sequence without any hardware modification and this ensures the compatibility of usual decoding system.

    Abstract Table of Contents List of Figure Chapter 1 Introduction 1.1 Stereo Video Technology 1.2 Motivation 1.3 Thesis organization Chapter 2 Overview on Stereo video system 2.1 Stereoscopic camera system 2.2 Revolution of 3D display 2.3 Stereo video coding process 2.4 Disparity estimation 2.5 H.264 based stereo video coding Chapter 3 Motion and disparity hybrid prediction for stereo video coding 3.1 H.264 based stereo video coding algorithm 3.1.1 Our proposed coding scheme 3.1.2 Main channel compensation and reconstruction 3.1.3 Auxiliary channel compensation and reconstruction 3.2 Architecture of disparity compensation 3.2.1 Disparity estimation architecture 3.2.2 Auxiliary channel block buffer 3.2.3 Auxiliary channel buffer management 3.2.4 Main channel buffer management 3.2.5 Process element and 2D PE array 3.2.6 Disparity vector generator 3.3 Architecture of disparity compensation 3.3.1 Disparity compensation architecture 3.3.2 Disparity prediction architecture Chapter 4 Simulation and Discussion 4.1 Algorithm simulation for hybrid prediction 4.2 Architecture simulation for disparity prediction 4.3 Xilinx FPGA platform simulation and demo Chapter 5 Conclusions and Future Works 5.1 Conclusions 5.2 Future works References

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    [12] Ding, L.-F.; Chien, S.-Y.; Chen, L.-G., “Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems”, IEEE Transactions on Circuits and Systems for Video Technology, Volume 16, Issue 11, Page(s):1324 – 1337, Nov. 2006.
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    [14] Xilinx, “Virtex-II Platform FPGA User Guide”, UG002 (v1.4) 1 November 2002.
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    [17] Iain E.G. Richardson, “H.264 and MPEG-4 Video Compression--Video Coding for Next-generation Multimedia”, John Wiley & Sons Ltd, 2003.

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