IEEE P1500基礎之SOC內嵌Delay Fault測試架構｜國立清華大學博碩士論文庫

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研究生：	邱灝軒 Hao-Hsuan Chiu
論文名稱：	IEEE P1500基礎之SOC內嵌Delay Fault測試架構 IEEE P1500 based SOC Delay Fault Testing Architecture
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	57
中文關鍵詞：	系統晶片、測試、延遲誤失測試、測試包裝、可測試設計
外文關鍵詞：	SoC, Testing, Delay-Fault Testing, Test Wrapper, DFT
相關次數：	點閱：1 下載：0
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摘要

隨著製程的演進，單一晶片上所能擁有的電晶體數目隨著晶片面積的增加以及最小長度的縮短而呈現非常快速的成長趨勢，製造一個上擁有數百萬至千萬的電晶體數目的晶片已不再是困難的事情。我們現在可以將一個完整的系統放入單一晶片的內部，這就是所謂的系統晶片(System On Chip)。以這樣的設計方法一個系統將可以被快速的建立。而在這樣的方法中，產生了兩個相對應的腳色，核心提供者(core provider)以及核心使用者(core user)。核心提供者提供設計好可以重新使用的核心，而核心使用者整合各個核心使其成立一個系統。這樣的設計概念衍生出的問題是如何對一個這樣的系統整合各個核心的測試資訊以及施行生產測試。目前已有數個為了解決核心測試整合時的問題的標準被提出來，希望能夠將低核心測試整合時的問題與所需要的努力。
基於現在的設計的時脈越來越高，在測試階段如何判斷一個產品是否有達到預定的時序要求也是越來越重要。對於系統晶片內部的核心的延遲誤失測試(Delay fault testing)即將會成為在製造測試中不可或缺的一環。然而目前已經提出的標準不是沒有考慮到延遲誤失測試就是無法滿足同時所有延遲誤失測試的需求以及系統晶片測試的成本。現存的架構並沒有辦法達到延遲誤失測試的時序精確度，或是因為此類測試的需求，而使各個核心的測試無法同時執行。在此篇論文中，我們提出一個新的系統晶片延遲誤失測試的架構，此架構包含了一個修改過後的P1500測試包裝架構(P1500 Test Wrapper Architecture)以及一個具有延遲誤失測試功能的時脈訊號控制器。修改過後的測試包裝能夠在單一的包裝下儲存一對測試圖案並精確的發送出測試圖案來達到延遲誤失測試的施行。時脈訊號控制器可以使得各個核心的測試不會互相干擾影響，降低測試所需時間。最後本文以一個現存的系統晶片來實際驗證新的測試架構的提供的功能性與可以接受的面積的消耗。

Abstract
Following the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The so-called system-on-chip design concept emphasizes reusability of building blocks and provides higher productivity. However, one of issues for the newly-emerging design concept is to verify the products’ functionality and timing specification. IEEE P1500 is applied to test functional correctness of each core in SOC. While verifying the timing specification, the existing wrapper is needed to be modified to carry out delay fault testing of individual core. In this thesis, a delay-fault-testing architecture that consists of modified wrapper based on IEEE P1500 standard and delay-test-aware clock controller is proposed. Wrapper is modified to recreate the environment of delay fault testing for embedded cores, while the clock controller is for test localization. The result shows acceptable area overhead in example SOC design.

Contents
Abstract    1
Contents    2
List of Figures    4
List of Tables    6
Chapter 1 Introduction    7
Chapter 2 Preliminaries    11
   2.1 IEEE P1500 Overview    11
      2.1.1 Core Test Language    11
      2.1.2 Scalable Core Test Architecture    11
   2.2 Delay Test Schemes and Requirements    13
   2.3 Previous Work    14
      2.3.1 Delay Fault Testing of Core-Based System-on-a-Chip    14
      2.3.2 Using the Oscillation Test Method to Test Delay Faults in Embedded Cores    17
Chapter 3 Wrapper Modification    20
   3.1 WBR Modification    21
      3.1.1 Input Part Modification    21
      3.1.2 Output Part Modification    22
   3.2 Control Circuitry Modification    23
   3.3 Explanation of Delay-Fault-Testing Sequence    24
   3.4 Reduction of pattern-pair shifting time    28
Chapter 4 Delay-Test-Aware Clock Controller    30
   4.1 Clock Switching Circuit    30
   4.2 Clock Control Cell    31
   4.3 Proposed Clock Controller    37
Chapter 5 Case Study    40
Chapter 6 Conclusions and Future Works    45
Bibliography    46

List of Figures
Fig. 2.1 Example of an IEEE P1500 SECT wrapper [5]    12
Fig. 2.2 Delay Test Schemes    14
Fig. 2.3 Producer/consumer model [4]    15
Fig. 2.4 Modified Wrapper for Oscillation Test Method    18
Fig. 3.1 IEEE P1500 WBR    22
Fig. 3.2 Input WBR    22
Fig. 3.3 Output WBR    23
Fig. 3.4 Modified Controller    24
Fig. 3.5 Waveform of Wrapper Setup Sequence    25
Fig. 3.6 Waveform of Phase 1 in Wrapper Test Sequence    26
Fig. 3.7 Waveform of Phase 2 in Wrapper Test Sequence    27
Fig. 3.8 Pattern Pair Shift Operation    28
Fig. 3.9 Alternate WBR    29
Fig. 3.10 Shift Operation with Alternate WBR    29
Fig. 4.1 Clock Gating Circuit    31
Fig. 4.2 Clock Switching Circuit    31
Fig. 4.3 CTRL_CELL    32
Fig. 4.4 FSM_T    32
Fig. 4.5 FSM_N    33
Fig. 4.6 Waveform of NORMALCLK Instruction    35
Fig. 4.7 Waveform of TESTCLK Instruction    36
Fig. 4.8 Waveform of Generation of Two Normal Clock Pulses    37
Fig. 4.9 Waveform of STALL Instruction    37
Fig. 4.10 SOC Example    38
Fig. 411 Clock Controller Configuration Relative to Example SOC    38
Fig. 5.1 Block Diagram of CP    40
Fig. 5.2 Test Architecture of CP    41

List of Tables
Table 3.1 Delay-Fault-Testing Sequence for Modified Wrapper    28
Table 5.1 DFT Summary of Cores    42
Table 5.2 Summary of Area of Cores in CP    43
Table 5.3 Result of Pattern Generation    43

                                

Bibliography

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