在面對越來越多的設計挑戰，如高設計複雜度、未成熟的新製程技術、緊迫的上市時間壓力等等，設計工程師必須將診斷跟除錯都視為設計過程的一部分。然而，隨著設計的尺寸增加，診斷的難度及其所必須花費的時間也隨之快速增加。診斷工具是用來快速的縮小可能發生缺陷的區域及數量，在不倚賴十分耗時物理檢視工具來一一檢查所以可能發生缺陷的地點，以利加快檢查出讓晶片或製程發生問題的原因。在先進製程上，時序缺陷(Timing defects)可能來自於許多方面，如由塵埃引起的短路缺陷(Short defects) 、由不適當的設計規範(DFM rules)所導致的開路缺陷(Open defects) 、由光學系統的透鏡不完美性所引發的透鏡像差、離子佈植不均和由不良的化學機械研磨過程(Chemical-Mechanical Polishing)導致的線寬不均等因素。因此，要從這麼多可能的原因中準確地判斷是由哪一個步驟或是發生的位置是非常困難。

在本論文中，我們針對了單點延遲缺陷及由製程變異所導致的微小延遲偏差提出了一系列的診斷相關技術及軟體。我們提出的方法除了如傳統的診斷方法可能產生一缺陷發生可能位置排序表外，並能夠估計晶片內部各個元件所能達到的速度。我們利用了這個優點，根據這些估計出來的元件效能，我們開發了一套能夠推算出在此製程下的晶片內部的時序圖像(Timing profile)。另外，我們也引用了統計學習的觀念來分析診斷後的資料，並且得到造成此製程變異的最可能因素。利用我們所提出的針對每個元件的特徵編碼(Feature encoding)及特徵排序方法，我們可以有效的收集資料並得到這些偏差的元件最主要的特徵。從這些特徵我們可以在設計時避免掉某些會造成製程變異的因素。在只植入單一個單點缺陷的實驗中，我們的方法能夠達到1.96 的平均排名，亦即我們平均在前兩名就能夠找到缺陷所在。而我們也做了同時植入10 個延遲缺陷的實驗，其平均排名為1.43。另外，針對製程變異所造成的微小延遲偏差，我們所提出的方法能夠準確的估計出每個元件的延遲時間。在實驗中，我們計算其估計出來跟由製程變異模型取樣出來的元件延遲時間的相關性，平均能夠達到高達0.916 的相關性，效果十分良好。

Facing a multitude of design constraints: higher design complexity, immature new process
technology, shrinking time-to-yield, etc., designers have to take debug and diagnosis as an integral
part of the design process. Yet, imposed by the huge design size, efforts of diagnosis increase
rapidly. Diagnosis tools are used to quickly shrink the number of defective candidates that helps
to speed up the process without resorting to physical inspection tool for every possible suspect
of faulty location. In advanced process, timing defects comes from several aspects such as dustinduced
short, open defects induced by in inappropriate Design For Manufacturability (DFM)
rules, lens aberration from lithography system, variation on dopant concentration or critical dimension
from Chemical-Mechanical Polishing (CMP) process, etc. Therefore, it is getting more
and more difficult to identify the main causes of timing failures from such a wide range of suspects.
In this thesis, we propose a series of diagnosis methods targeting on not only spot delay defects
but small delay variation induced by process variation. The proposed method is capable of
estimating delays of segments in tested paths instead of just reporting the ranks of segments as the
traditional diagnosis methods. With the capability, a timing profile for the process and the die under
manufacturing can be extracted based on the estimated segment delays. Moreover, the causes
of process variation can be concluded by applying machine learning techniques on diagnosis data.
With the proposed feature encoding and ranking method, the main features of abnormal devices
for a failing chip instance can be extracted. In the experiments, 1.96 of first-hit-rate (ranking of the
injected defects) for single spot defects and 1.43 of first-hit-rate for 10 spot defects simultaneously
injected can be achieved For process variation induced small delay variations, the proposed method
can provide an accurate estimation of segment delays. On average, 0.916 of correlation between
estimated and sampled segment delays for a dozen of benchmarks.

[1] A. Krstic, L. C.Wang, J. J. Liou, and M. S. Abadir, “Diagnosis-based post-silicon timing validation
using statistical timing tools and methodologies,” Proceedings of IEEE International
Test Conference, pp. 339–348, 2003.
[2] Y.-Y. Chen and J.-J. Liou, “Extraction of statistical timing profiles using test data,” Proceedings
of Design Automation Conference, pp. 509–514, June 2007.
[3] P. Girard, C. Landrault, and S. Pravossoudovitch, “A Novel Approach to Delay-Fault Diagnosis,”
Proceedings of Design Automation Conference, pp. 357–360, June 1992.
[4] H. B. Wang, S. Y. Huang, and J. R. Huang, “Gate-delay fault diagnosis using the inject-andevaluate
paradigm,” Proceedings of International Symposium on Defect and Fault Tolerance
in VLSI Systems, pp. 117–125, Nov. 2002.
[5] J. Ghosh-Dastidar and N. A. Touba, “A systematic approach for diagnosing multiple delay
fauls,” Proceedings of Defect and Fault Tolerance in VLSI System, pp. 211–216, Nov. 1998.
[6] ——, “Adaptive techniques for improving delay fault diagnosis,” Proceedings of IEEE VLSI
Test Symposium, pp. 168–172, Apr. 1999.
[7] O. Poku and R. D. Blanton, “Delay defect diagnosis using segment network faults,” Proceedings
of IEEE International Test Conference, pp. 1–10, Oct. 2002.
[8] Z. Wang, M. M. Marek-Sadowska, K. H. Tsai, and J. Rajski, “Delay-fault diagnosis using
timing information,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, pp. 1315–1325, Sept. 2005.
104
[9] A. Krstic, L. C. Wang, J. J. Liou, and M. S. Abadir, “Delay defect diagnosis based upon
statistical timing models,” Proceedings of Design, Automation and Test in Europe, pp. 328–
333, 2003.
[10] A. Krstic, L. C. Wang, J. J. Liou, and T. M. Mak, “Enhancing diagnosis resolution for delay
defects based upon statistical timing and statistical fault models,” Proceedings of Design
Automation Conference, pp. 668–673, June 2003.
[11] A. Krstic, L. C.Wang, K. T. Cheng, and J. J. Liou, “Diagnosis of delay defects using statistical
timing models,” Proceedings of IEEE VLSI Test Symposium, pp. 339–344, 2003.
[12] P. Pant and A. Chatterjee, “Efficient Diagnosis of Path Delay Faults in Digital Logic Circuits,”
Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 471–
475, Nov. 1999.
[13] P. Pant, Y.-C. Hsu, S. K. Gupta, and A. Chatterjee, “Path Delay Fault Diagnosis in Combinational
Circuits With Implicit Fault Enumeration,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, pp. 1226–1335, Oct. 2001.
[14] R. C. Tekumalla, S. Venkataraman, and J. G. Dastidar, “On Diagnosing Path Delay Fault
in an At-Speed Environment,” Proceedings of IEEE VLSI Test Symposium, pp. 28–33, Apr.
2001.
[15] S. Padmanaban and S. Tragoudas, “An Implicit Path-Delay Fault Diagnosis Methodology,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1399–
1408, Oct. 2003.
[16] ——, “An adaptive path delay fault diagnosis methodology,” Proceedings of International
Symposium on Quality Electronic Design, pp. 491–496, 2004.
[17] M. Sivaraman and A. J. Strojwas, “Path delay fault diagnosis and coverage-a metric and an
estimation technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, pp. 440–457, Mar. 2001.
105
[18] ——, “Diagnosis of parametric path delay faults,” Proceedings of International Conference
on VLSI Design, pp. 412–417, 1995.
[19] ——, “Diagnosis of path delay faults,” Proceedings of the Midwest Symposium on Circuits
and Systems, pp. 769–772, 1996.
[20] Y.-C. Hsu and S. K. Gupta, “A New Path-Oriented Effect-Cause Methodology to Diagnose
Delay Failures,” Proceedings of IEEE International Test Conference, pp. 758–767, Oct. 1998.
[21] A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process
variation with spatial correlations,” Proceedings of IEEE/ACM International Conference on
Computer-Aided Design, 2003.
[22] H. Chang and S. Sapatnekar, “Statistical timing analysis considering spatial correlations
using a single pert-like traversal,” Proceedings of IEEE/ACM International Conference on
Computer-Aided Design, Nov. 2003.
[23] L. Zhang, W. Chen, Y. Hu, J. A. Gubner, and C.-P. Chen, “Correlation-preserved non-
Gaussian statistical timing analysis with quadratic timing model,” Proceedings of Design
Automation Conference, June 2005.
[24] Y. Zhan, A. J. Strojwas, X. Li, L. T. Pileggi, D. Newmark, and M. Sharma, “Correlation-aware
statistical timing analysis with non-Gaussian delay distributions,” Proceedings of IEEE/ACM
International Conference on Computer-Aided Design, Nov. 2005.
[25] Bhardwaj, P. Ghanta, and S. Vrudhula, “A framework for statistical timing analysis using
non-linear delay and slew models,” Proceedings of IEEE/ACM International Conference on
Computer-Aided Design, Nov. 2006.
[26] S. W. Director and G. D. Hachtel, “The simplicial approximation approach to design centering,”
IEEE Transactions on Circuits and Systems, vol. 24, no. 7, pp. 363–372, July 1977.
[27] K. K. Low and S. W. Director, “A new methodology for the design centering of IC fabrication
processes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 10, no. 7, pp. 895–903, July 1991.
106
[28] G. S. Samudra, H. M. Chen, D. S. H. Chan, and Y. Ibrahim, “Yield optimization by design
centering and worst-case distance analysis,” Proceedings of IEEE International Conference
on Computer Design, 1999.
[29] O. Neiroukh and X. Song, “Improving the process-variation tolerance of digital circuits using
gate sizing and statistical techniques,” Proceedings of Design, Automation and Test in Europe,
Apr. 2005.
[30] S. H. Kulkarni, D. Sylvester, and D. Blaauw, “A statistical framework for post-silicon tuning
through body bias clustering,” Proceedings of IEEE/ACM International Conference on
Computer-Aided Design, Nov. 2006.
[31] M. Mani, A. K. Singh, and M. Orshansky, “Joint design-time and post-silicon minimization
of parametric yield loss using adjustable robust optimization,” Proceedings of IEEE/ACM
International Conference on Computer-Aided Design, Nov. 2006.
[32] D. Boning, T. Maung, J. Chung, K.-J. Chang, S.-Y. Oh, and D. Bartelink, “Statistical metrology
of interlevel dielectric thickness variation,” SPIE Symposium on Microelectronic Manufacturing,
1994.
[33] C. Yu, T. Maung, C. Spanos, D. Boning, J. Chung, H. Y. Liu, K. J. Cheng, and D. Bartelink,
“Use of Short-Loop Electrical Measurements for Yield Improvement,” IEEE Transactions on
Semiconductor Manufacturing, vol. 8, no. 2, May 1995.
[34] S. Y. Oh, W. Y. Jung, J. T. Kong, and K. H. Lee, “Interconnect Modeling in Deep Submicron
Design,” IEEE International Conference on VLSI and CAD, 1999.
[35] J. Lee, K. Lee, J. K. Park, J. B. Lee, Y. K. Park, J. T. Kong, O. Y. Jung, and S. Y. Oh, “An
indirect extraction of interconnect technology parameters for efficient statistical interconnect
modeling and its applications,” IEEE International Workshop on Statistical Metrology, 2000.
[36] N. D. Arora and L. Song, “Atto-Farad Measurement and Modeling of On-Chip Coupling
Capacitance,” IEEE Electron Device Letters, vol. 25, no. 2, Feb. 2004.
[37] A. C. Diebold, Handbook of Silicon Semiconductor Metrology. New York, NY: CRC, 2001.
107
[38] Z. Lin, C. J. Spanos, L. S. Milor, and Y. T. Lin, “Circuit sensitivity to interconnect variation,”
IEEE Transactions on Semiconductor Manufacturing, vol. 11, no. 4, pp. 557–568, Nov. 1998.
[39] N. Abaskjaroun and G. W. Roberts, “Circuits for on-chip sub-nanosecond signal capture and
characterization,” Proceedings of Custom Integrated Circuits Conference, 2003.
[40] P. yang Yan, Q.-D. Qian, and J. C. Langston, “Effect of lens aberration on obliqueillumination
stepper system,” Proceedings of SPIE, pp. 167–180, Aug. 1993.
[41] T. Brunner, “Impact of lens aberrations on optical lithography,” IBM Journal of Research and
Development, pp. 57–67, 1997.
[42] R. T. Schmidt, C. A. Spence, L. Capodieci, Z. Krivokapic, B. Geh, and D. G. Flagello, “Impact
of coma on CD control for multiphase PSM designs,” Proceedings of SPIE, pp. 15–24,
June 1998.
[43] S. P. Renwick, “Flare and its effects on imaging,” Proceedings of SPIE, pp. 442–450, May
2004.
[44] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Boston, MA: Kluwer
Academic Publishers, 1998.
[45] B. Chess and T. Larrabee, “Creating small fault dictionaries,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 346–356,
Mar. 1999.
[46] I. Pomeranz and S. M. Reddy, “On the generation of small dictionaries for fault location,”
Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 1992.
[47] W. M. Lee, M. Paniccia, T. Eiles, and V. Rao, “Laser voltage probe (LVP): a novel optical
probing technology for flip-chip packaged microprocessors,” Proc. IPFA, 1999.
[48] C. Burmer, R. Guo, W.-T. Cheng, X. Lin, and B. Benware, “Timing failure debug using
debug-friendly scan patterns and tre,” International Symposium for Testing and Failure Analysis,
Nov. 2008.
108
[49] J. C. Tsang, J. A. Kash, and D. P. Vallett, “Time-resolved optical characterization of electrical
activity in integrated circuits”,” Proceedings of IEEE International Test Conference, 2000.
[50] K. Nikawa and S. Tozaki, “Novel obic observation method for detecting defects in a1 stripes
uder current stressing,” International Symposium for Testing and Failure Analysis, 1993.
[51] V. Mehrotra, “Modeling the effects of systematic variation on circuit performance,” Ph.D.
dissertation, Dept. EECS, Massachusetts Institute of Technology, 2001.
[52] R. Chang, Y. Cao, and C. J. Spanos, “Modeling the electrical effects of metal dishing due to
cmp for on-chip interconnect optimization,” IEEE Transactions on Electron Devices, vol. 51,
no. 10, Oct. 2004.
[53] K. Agarwal and S. Nassif, “Characterizing process variation in nanometer cmos,” Proceedings
of Design Automation Conference, pp. 396–399, June 2007.
[54] B. Zhou and A. Khouas, “Measurement of delay mismatch due to process variations by means
of modified ring oscillators,” Proceedings of International Symposium on Circuits and Systems,
pp. 5246–5248, May 2005.
[55] A. Bassi, A. Veggetti, L. Croce, and A. Bogliolo, “Measuring the effects of process variations
on circuit performance by means of digitally-controllable ring oscillators,” International Conference
on Microelectronic Test Structures, pp. 214–217, Mar. 2003.
[56] M. Nourani and A. Redhakrishnan, “Modeling and testing process variation in nanometer
cmos,” Proceedings of IEEE International Test Conference, 2006.
[57] D. Boning, T. Maung, J. Chung, K.-J. Chang, and S.-Y. O. an D. Bartelink, “Statistical metrology
of interlevel dielectric thickness variation,” Proceedings of SPIE, 1994.
[58] D. Boning and J. Chung, “Statistical metrology: understanding spatial variation in semiconductor
manufacturing,” Proceedings of SPIE, 1996.
[59] B. Stine, V. Mehrotra, D. Boning, J. Chung, and D. Ciplickas, “A simulation methodology for
accessing the impact of spatial/pattern dependent interconnect parameter variation on circuit
performance,” International Electron Devices Meeting, 1997.
109
[60] V. Mehrotra, S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif, “A
methodology for modeling the effect of systematic within-die interconnect and device variation
on circuit performance,” 2000.
[61] D. Appello, A. Fudoli, K. Giarda, E. Gizdarski, B. Mathew, and V. Tancorre, “Yield analysis
of logic circuits,” Proceedings of IEEE VLSI Test Symposium, 2004.
[62] L.-C. Wang, P. Bastani, and M. S. Abadir, “Design-silicon timing correlation-a data mining
perspective,” Proceedings of Design Automation Conference, pp. 384–389, June 2007.
[63] P. Bastani, N. Callegari, L.-C.Wang, and M. S. Abadir, “An improved feature ranking method
for diagnosis of systematic timing uncertainty,” IEEE International Symposium on VLSI Design,
Automation and Test, pp. 101–104, Apr. 2008.
[64] ——, “Diagnosis of design-silicon timing mismatch with feature encoding and importance
ranking – the methodology explained,” Proceedings of IEEE International Test Conference,
pp. 1–10, 2008.
[65] M. Sharma, B. Benware, L. Ling, D. Abercrombie, L. Lee, M. Keim, H. Tnag, W.-T. Cheng,
T.-P. Tai, Y.-J. Change, R. Lin, and A. Man, “Efficiently performing yield enhancements by
identifying dominant physical root cause from test fail data,” Proceedings of IEEE International
Test Conference, 2008.
[66] D. Dumas, P. Girard, C. Landrault, and S. Pravossoudovitch, “Effectiveness of a variable
sampling time strategy for delay fault diagnosis,” Proceedings of European Design and Test
conference, pp. 518–523, Mar. 1994.
[67] W. Mao and M. D. Ciletti, “A variable observation time method for testing delay faults,”
Proceedings of Design Automation Conference, pp. 728–731, June 1990.
[68] R. Tayade and J. A. Abraham, “On-chip programmable capture for accurate path delay test
and characterization,” Proceedings of IEEE International Test Conference, pp. 1–10, Oct.
2008.
110
[69] H.-J. Hsu, C.-C. Tu, and S.-Y. Huang, “Built-in speed grading with a process tolerant adpll,”
Proceedings of IEEE Asian Test Symposium, pp. 384–392, Oct. 2007.
[70] Y. Y. Chen, M. P. Kuo, and J. J. Liou, “Diagnosis framework for locating failed segments
of path delay faults,” Proceedings of IEEE International Test Conference, pp. 387–394, Nov.
2005.
[71] W. K. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Delay fault
coverage and performance tradeoffs,” Proceedings of Design Automation Conference, pp.
446–452, June 1993.
[72] K. T. Cheng and H. C. Chen, “Delay testing for nonrobust untestable circuits,” Proceedings
of IEEE International Test Conference, pp. 954–961, Apr. 1993.
[73] U. Sparmann, D. Luxenburger, K. T. Cheng, and S. Reddy, “Fast identification of robust
dependent path delay faults,” Proceedings of Design Automation Conference, pp. 119–125,
June 1995.
[74] J. J. Liou, K. T. Cheng, and D. A. Mukherjee, “Path Selection for Delay Testing of Deep Sub-
Micron Devices Using Statistical Performance Sensitivity Analysis,” Proceedings of IEEE
VLSI Test Symposium, pp. 97–104, Apr. 2000.
[75] P. Notebaert, “Linear programming solver,” http://groups.yahoo.com/group/lpsolve, 2003.
[76] J. J. Liou, A. Krstic, L. C.Wang, and K. T. Cheng, “False-path-aware statistical timing analysis
and efficient path selection for delay testing and timing validation,” Proceedings of Design
Automation Conference, pp. 566–569, June 2002.
[77] J. J. Liou, A. Krstic, K. T. Cheng, D. Mukherjee, and S. Kundu, “Performance sensitivity
analysis using statistical methods and its applications to delay testing,” Proceedings of Asia
& South Pacific Design Automation Conference, pp. 587–592, Jan. 2000.
[78] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda,
“Statistical delay computation considering spatial correlations,” Proceedings of Asia & South
Pacific Design Automation Conference, 2003.
111
[79] Q. Liu and S. S. Sapatnekar, “Confidence scalable post-silicon statistical delay prediction
under process variations,” Proceedings of Design Automation Conference, pp. 497–502, June
2007.
[80] P. Camurati, A. Lioy, P. Prinetto, and M. S. Reorda, “Diagnosis oriented test pattern generation,”
Proceedings of European Design and Test conference, pp. 470–474, Mar. 1990.
[81] F. Corno, P. Prinetto, M. Rebaudengo, and M. S. Reorda, “GARDA:a diagnostic ATPG for
large synchronous sequential circuits,” Proceedings of European Design and Test conference,
pp. 267–271, Mar. 1995.
[82] P. Girard, G. Landrault, S. Pravossoudovitch, and B. Rodriguez, “A diagnostic ATPG for
delay faults based on genetic algorithm,” Proceedings of IEEE International Test Conference,
pp. 286–293, Oct. 1996.
[83] R. C. Tekumalla, “On test set generation for efficient path delay fault diagnosis,” Proceedings
of IEEE VLSI Test Symposium, pp. 343–348, May 2000.
[84] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd.
The MIT Press, 2001.
[85] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits. Boston: Kluwer Academic
Publishers, 1999.
[86] M. Sharma and J. H. Patel, “Bounding Circuit Delay by Testing a Very Small Subset of
Paths,” Proceedings of IEEE VLSI Test Symposium, pp. 333–341, Apr. 2000.
[87] T. Sergios and K. Koutroumbas, Pattern recognition, 2nd ed. San Diego: Academic Press,
2003.
[88] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda,
“Statistical delay computation considering spatial correlations,” Proceedings of Asia & South
Pacific Design Automation Conference, 2003.
112
[89] J. He, A.-H. Tan, C.-L. Tan, and S.-Y. Sung, “On quantitative evaluation of clustering systems,”
in Information Retrieval and Clustering, W. Wu and H. Xiong, Eds. Kluwer Academic
Publishers, 2002, in press.
[90] C. M. Bishop, Pattern recognition and machine learning. New York: Springer, 2006.
[91] Y.-W. Chang and C.-J. Lin, “Feature ranking using linear SVM,” JMLR: Workshop and Conference
Proceedings, 2008.
[92] B. E. Boser, I. Guyon, and V. Vapnik, “A training algorithm for optimal margin classifier,”
Proceedings of the Fifth Annual Workshop on Computational Learning Theory, pp. 144–152,
1992.
[93] C.-W. Hsu, C.-C. Chang, and C.-J. Lin, “A partical guide to support vector classification,”
2009, document available at http://www.csie.ntu.edu.tw/cjlin/papers/guide/guide.pdf.
[94] I. Guyon, J. Weston, S. Barnhill, and V. Vapnik, “Cancer classification using support vector
machines,” Machine Learning Journal, vol. 46, pp. 389–422, Jan. 2002.
[95] M.-C. Wu, “An aerial image simulator for fast critical dimension estimation of lithography
process,” Master’s thesis, EE Dept., National Tsing-Hua University, Jan. 2008.
[96] J. W. Goodman, Introduction to Fourier Optics. Englewood, Colo.: Roberts & Co, 2005.
[97] K.-M. Chang, “Analysis of systematic variation for path delay and critical area with lithography
simulation,” Master’s thesis, EE Dept., National Tsing-Hua University, Jan. 2009.
[98] C.-C. Chang and C.-J. Lin, LIBSVM: a library for support vector machines, 2001, software
available at http://www.csie.ntu.edu.tw/cjlin/libsvm.