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研究生： 王崇滕
Wang, Chong-Teng
論文名稱： RISC-V向量擴展指令集在Gem5的模擬及驗證
Gem5 Simulation and Verification for RISC-V Vector Extension
指導教授： 李政崑
Lee, Jenq-Kuen
口試委員: 黃冠寰
Hwang, Gwan-Hwan
張峯銘
Chang, Feng-Ming
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2024
畢業學年度： 112
語文別： 英文
論文頁數： 41
中文關鍵詞： RISC-V 、向量擴展指令集 、RVV intrinsic 、gem5模擬器 、半精度浮 點數
外文關鍵詞： RISC-V, Vector extension, RVV intrinsic, The gem5 Simulator, FP16
相關次數： 點閱：47  下載：4 
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    • 本研究探討並驗證了RISC-V向量擴充指令集（RVV）在gem5模擬器上的實作。gem5是一個用於電腦系統架構研究的平台。與其他模擬器不同，gem5提供cycle-level的模擬，這對於精確模擬RVV指令至關重要，特別是對於機器學習或雲端運算等高資料級平行性工作負載而言。本研究的主要貢獻在於提出了gem5上RVV指令的修正方案，並實作了Zvfh和Zvfhmin，這是支援FP16標準的向量擴充指令集。
    實作的驗證使用了遵循RISC-V Compatibility Framework（RISCOF）測試格式規範的RISC-V架構測試。除此之外，本研究還包括在gem5上開發超長指令字（VLIW）架構，以同時利用指令級和資料級平行性的優勢。
    提出的修正方案已經修正了gem5上的995條RVV指令，每條指令都有不同的LMUL和SEW設定。

    This thesis discusses and verifies the implementation of the RISC-V Vector Extension (RVV) on the gem5 simulator, a platform for computer-system architecture research. Unlike other simulators, gem5 offers cycle-level simulation, crucial for accurately simulating RVV instructions, especially for high data-level parallelism workloads like machine learning or cloud computing. The thesis’s main contributions are the proposed fixes for the RVV instructions on gem5 and the implementation of Zvfh and Zvfhmin, which are standard vector extension with FP16 support. The implementation’s verification uses RISC-V architectural tests following the RISC-V Compatibility Framework (RISCOF) Test Format Spec. The thesis also includes developing a Very Long Instruction Word (VLIW) architecture on gem5 to leverage both instruction-level and data-level parallelism benefits. The proposed fixes have corrected 995 RVV instructions on gem5, each with different LMUL and SEW settings.

    1 Introduction 1 2 Background 4 2.1 RISC-V Vector Extension 4 2.2 Simulator 5 2.2.1 Spike 5 2.2.2 The gem5 Simulator 5 2.3 RISCOF Framework 6 2.4 VLIW 7 3 The gem5 Simulator Verification 9 3.1 Verification workflow 9 3.1.1 TestFormatSpec 11 3.2 Simulation 13 3.2.1 Decoding and Execution of Instruction 13 3.2.2 Additional Assembly Macro 15 3.3 Implementation Correction 16 3.3.1 Fix issue when vl=0 in VectorIntMaskMacroConstructor 17 3.3.2 Fix load and store to use EEW instead of SEW 18 3.3.3 Fix vsadd and vsaddu 19 3.3.4 Fix narrowing/widening type-convert instructions 19 3.3.5 Fix viota instruction 22 3.4 FP16 Implementation 26 4 VLIW Simulation 30 4.1 Simulation Model 30 4.2 Implementation 30 5 Experiment 34 5.1 Environment 34 5.2 RISC-V Architectural TestSuite for Vector Extension 35 6 Conclusion 37 Bibliography 39

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