在單晶片(SoC)系統的設計上，半導體記憶元件的比重越來越大，因此，半導體記憶元件的測試也日驅重要，隨著半導體記憶元件的面積與速度快速地增加，所需使用的測試時間與測試電路也越來越大。在這篇碩士論文中，我們針對在半導體記憶元件的測試中兩種不同的問題，提出不同的解決方法，第一個問題是關於縮短半導體記憶元件測試時間的方法，另一個事關於快閃式記憶體之自我測試電路產生器。

第一部份，我們提出了一個有系統的方式來縮短半導體記憶元件的測試時間，經由分析與重新整理整體的測試流程，我們可以將原有的測試項目作合併，也可以利用模擬器來發展新的測試項目以增加錯誤涵蓋率(fault coverage)。這個有效率之測試項目可以取代原始的測試項目，節省半導體記憶元件整體的測試時間，而在實驗結果中，證實了所提出之測試項目在不影響整體之錯誤涵蓋率的情況下，有效節省了7%的測試時間。

第二部份，我們提出了一個用於快閃式記憶體的自我測試電路產生器，這個自我測試電路產生器可以根據快閃式記憶體的規格與測試的要求來產生可合成的自我測試電路，並且，自我測試電路的架構將會合併我們以前所作的快閃式記憶體的架構與之前所發展的內嵌式隨機存取記憶體之自我測試電路產生器(稱作BRAINS)的架構，並且提供可程式化的March-like 測試演算法。這個快閃記憶體的自我測試電路產生器可縮短測試電路的設計時間，並且，使用我們所提出的
架構可以方便測試排程(test scheduling)的控制。

Semiconductor memories play an important role in modern System-on-Chip (SoC) designs, including RAM and Flash memory. Semiconductor memory testing thus has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion—which is expensive and more and more difficult to keep up with the memory capacity growth—is a long time researched issue, as test cost is directly related to the time each
product stays on the tester. Furthermore, we also need more design-for-testability (DFT) circuits to reduce the memory test time in the SoC era. The designers need to pay more attention to designing the DFT circuits.

In this thesis, there are two parts devoted solving the memory testing issues discussed above. One is semiconductor memory test time reduction. We propose a systematic pproach to analying and rearranging the test items in the test flow. We propose two test compaction techniques: 1) merging existing test patterns, 2) developing efficient new test patterns. The proposed test time reduction algorithm is shown to effectively reduce the test time of an industrial DRAM test flow. The test time reduction tool also can identify the redundant test items, suggest a proper test list, and provide the correlation between the test items. In the industrial case, an extra 7% of the total test time is further reduced, on top of the original manually compacted test flow.

The other is the Flash memory built-in self-test (BIST) circuit generator. This generator can generate synthesizable BIST RTL code in Verilog, and the generated BIST can combine with RAM BIST that is generated by a RAM BIST generator (called BRAINS). Besides, the generated BIST
architecture supports paralled testing of multiple Flash memory cores to reduce test time in SoC.

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