適用於物聯網之超高能源效率之高解析度類比數位轉換器

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研究生：	謝頌恩 Hsieh, Sung-En
論文名稱：	適用於物聯網之超高能源效率之高解析度類比數位轉換器 High Resolution ADC with Ultra-High Power Efficiency for IoT Application
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	張順志 Chang, Soon-Jyh 李泰成 Lee, Tai-Cheng 洪浩喬 Hong, Hao-Chiao 許雲翔 Shu, Yun-Shiang 謝秉璇 Hsieh, Ping-Hsuan 陳信樹 Chen, Hsin-Shu 黃柏鈞 Huang, Po-Chiun
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	107
語文別：	英文
論文頁數：	152
中文關鍵詞：	低電壓、低功耗、高解析度、連續漸進式類比數位轉換器、積分微分調變器
外文關鍵詞：	low voltage, low power, high resolution, SAR ADC, SDM
相關次數：	點閱：4 下載：0
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在物連網的應用蓬勃發展下，為了達到更智慧化的系統及社會，無所不在的感知層和大量無線感測節點是無可避免的，但是大量的無線感測節點，會造成整體系統功耗過大。因此，本論文提出了三種低功耗的類比數位轉換器，提供環境能量擷取的可能性。
本論文第一個提出的電路為操作在0.3伏十位元的連續漸進式類比數位轉換器。在現今的連續漸進式類比數位轉換器的實現上，往往數位電路的硬體功耗會是最大的負擔，利用提出的電容陣列切法，在數位電路的實作上將都會是單端操作，降低其中節點所需要的充放電次數，以降低數位功耗。此轉換器在台積電90奈米製造，取樣頻率為每秒二十五萬次取樣，有效位元數8.21位元，整體換算的性能表現為0.705 fJ/conversion-step.
本論文的第二個晶片設計為操作低壓0.3伏的連續漸進式類比數位轉換器。在上個晶片的實作中發現，在超低壓的設計下，雜訊的干擾就會顯得惡化，造成無法有效提升有效位元數，所以此架構在比較器上提出了低功耗、低雜訊的做法，也在切換方法有所改良，達到更高的輸入訊號範圍，以降低整體系統雜訊。此晶片使用台積電90奈米製造，取樣頻率為每秒六十萬次取樣，有效位元數為9.46位元，整體換算性能表現為0.44 fJ/conversion-step。
本論文的第三個晶片設計提出混和式的類比數位轉換器，前端為連續漸進式類比數位轉換器，後端為Sigma-delta modulator。根據過往的研究，發現如果想要再進一步提升解析度，電容陣列的準度需要提升，以提升系統線性度，並且必須採用sigma-delta modulator之架構來有效壓抑熱雜訊。第三個晶片設計因此提出提升線性度之電容陣列切換方式，和使用了sigma-delta modulator降低雜訊。此晶片使用台積電90奈米製造，取樣頻率為每秒二十七萬次取樣，有效位元數為11.93位元，整體換算性能表現為0.606 fJ/conversion-step。

With the extensive growing of Internet-of-Things (IoT), in order to achieve the function of smart grids, densely existing sensing nodes and ubiquitous devices become inevitable. While the existence of sensing nodes grows exponentially, dramatically increased power consumption becomes unbearable. To address this problem, this paper proposes three ultra-low power analog to digital converters which provide possibilities for an energy harvesting technique.
The first architecture is a 0.3 V 10-bit successive approximation register analog-to-digital converter. With advanced switching procedures and efficient analog techniques, digital circuit’s power consumption becomes the dominant factor for the overall system’s power efficiency. With the proposed switching procedure, the realization of digital circuits is single-ended, which reduces dynamic power consumption (CV2) of internal nodes. This chip is fabricated under the TSMC 90 nm technology. The sampling rate is 250 kSamples/second. The effective number of bit is 8.21 bits. The Walden’s FoM is 0.705 fJ/conversion-step.
The second architecture is still a 0.3 V successive approximation register analog-to-digital converter. From the experience of the previous implementation, ADC suffers from thermal noise due to the decreasing VLSB from a shrinking supply voltage. Therefore, this work proposes a low noise comparator. With proposed input range boosting switching procedure, the full input range is doubled, which results in suppressed thermal noise. This chip is fabricated under the TSMC 90 nm technology. The sampling rate is 600 kSamples/second. The effective number of bit is 9.46 bits. The Walden’s FoM is 0.44 fJ/conversion-step.
The last implementation is a hybrid analog-to-digital converter, it uses a successive approximation register analog-to-digital converter and Sigma-delta modulator as coarse and fine ADCs, respectively. From the previous study, the matching performance of the capacitor array must be improved. Furthermore, the Sigma-delta modulator must be adopted to suppress thermal noise. This work proposes a switching procedure which increases the linearity. Furthermore, a sigma-delta modulator is implemented. This chip is fabricated under the TSMC 90 nm technology. The sampling rate is 270 kSamples/second. The effective number of bit is 11.93 bits. The Walden’s FoM is 0.606 fJ/conversion-step.

CONTENTS
ABSTRACT    III
CONTENTS    VII
LIST OF FIGURES    XII
LIST OF TABLES    XVIII
CHAPTER 1    INTRODUCTION    1
1    MOTIVATION    1
2    THESIS ORGANIZATION    3
CHAPTER 2    FUNDAMENTALS OF ADC    5
1    NYQUIST THEOREM    5
2    RESOLUTION    6
3    OFFSET ERROR    6
4    GAIN ERROR    7
5    QUANTIZATION ERROR    8
6    SIGNAL-TO-NOISE RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB)    10
7    SIGNAL-TO-NOISE AND DISTORTION RATIO (SNDR)    11
8    EFFECTIVE NUMBER OF BITS (ENOB)    11
9    DIFFERENTIAL NONLINEARITY (DNL)    12
10    INTEGRAL NONLINEARITY (INL)    13
11    SPURIOUS-FREE DYNAMIC RANGE (SFDR)    14
12    FIGURE OF MERIT (FOM)    14
CHAPTER 3    OVERVIEW OF ADCS    16
1    TOP-LEVEL DISCUSSIONS    16
1.1    SAR ADC    16
1.2    Sigma-Delta Modulator (DSM or SDM)    18
1.3    Incremental Sigma-Delta Modulator (ISDM)    21
2    SAMPLE AND HOLD (S/H) CIRCUITS    23
2.1    Sampling Speed    23
2.2    Signal Dependent Resistance    24
2.3    Charge Injection    25
2.4    Clock Feedthrough    26
3    DIGITAL-TO-ANALOG CONVERTER WITH THE CAPACITIVE ARRAY    27
3.1    Parasitic Capacitance    29
3.2    Mismatch    29
3.3    kT/C noise    30
4    COMPARATOR    30
4.1    Input-referred offset    32
5    SUMMARY    32
CHAPTER 4    CHALLENGES OF ULTRA-LOW VOLTAGE OPERATIONS    34
1    DIGITAL CIRCUIT    35
2    SAMPLE AND HOLD    39
3    COMPARATOR    42
4    CDAC    45
5    SUMMARY    47
CHAPTER 5    A 0.3V 0.705FJ/CONVERSION-STEP 10-BIT SAR ADC WITH SHIFTED MONOTONIC SWITCHING PROCEDURE IN 90NM CMOS    50
1    INTRODUCTION    50
2    PROPOSED ADC ARCHITECTURE    53
2.1    Shifted Monotonic switching procedure (SMS)    54
2.2    Dynamic comparator offset    58
2.3    Noise Performance    60
2.4    Redundancy implementation    63
3    CIRCUITS IMPLEMENTATION    64
3.1    Body driven switches    64
3.2    Layout implementation of CDAC    65
4    MEASUREMENT RESULT    66
5    SUMMARY    69
CHAPTER 6    A 0.44 FJ/CONVERSION-STEP 11B 600 KS/S SAR ADC WITH SEMI-RESTING DAC    71
1    INTRODUCTION    72
2    PROPOSED SAR ADC ARCHITECTURE    76
2.1    Semi-resting (SR) Switching Procedure    78
2.2    Digital Foreground Calibration    80
2.3    Switching energy    82
2.4    Nonlinearity    86
3    IMPLEMENTATION OF KEY BUILDING BLOCKS    88
3.1    Double-Bootstrapped Sample-and-Hold    88
3.2    Cascade-Input Comparator    90
3.3    Capacitor Array Arrangement    94
4    MEASUREMENT RESULTS    96
5    SUMMARY    101
CHAPTER 7    A 0.4V 13-BIT 270KS/S SAR-ISDM ADC WITH OPAMP-LESS TIME-DOMAIN INTEGRATOR    104
1    INTRODUCTION    105
2    PROPOSED SAR ADC ARCHITECTURE    107
2.1    Proposed SAR ADC Architecture    111
2.2    Switching Energy and Specification of Reference Buffer    114
2.3    Nonlinearity    116
3    IMPLEMENTATION OF KEY BUILDING BLOCKS    118
3.1    Voltage-Controlled Delay Line (VCDL) and ISDM    118
3.2    Non Ideal Effects of VCDL for the ISDM Operation    125
3.3    Vcm Sensitivity of INLS Switching Procedure    126
3.4    Capacitor Array Arrangement    128
3.5    Detailed Arrangements of Redundancy    128
4    MEASUREMENT RESULTS    130
5    SUMMARY    134
CHAPTER 8    CONCLUSIONS OF LOW-V OPERATIONS AND FUTURE WORKS    137
1    STATE-OF-THE-ART WORKS    137
2    PROPOSED WORKS    141
3    FUTURE WORK    142
PUBLICATION LIST    144
JOURNAL    144
CONFERENCE    144
BIBLIOGRAPHY    146


                                

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