本篇論文主要描述一個應用在FHD影像感測器上的類比數位轉換器，為了達到多行感測器共用一個轉換器，本碩論預計每200個 column的感測器共用一個類比數位轉換器，轉換器的規格為12位元且取樣頻率為20MHz，並且在架構上採用兩階段連續漸進式類比數位轉換器，而連續漸進式轉換器最引人詬病的地方在於本身電容面積過大，因此本篇論文在電容面積上有大幅的縮減。兩階式轉換器相較於傳統的連續漸進式優勢在於保持相同的取樣頻率下，本篇論文的兩階式電容面積為傳統電容面積的1/16 (以12位元為例 )，在面積上節省不少。

　　此設計在TSMC 0.18 um 1P6M CMOS製程下加以實現，晶片總面積包含TSMC 的ESD I/O pad為 1.109mm2，此類比數位轉換器的供應電壓為1.8V、取樣頻率20M Hz，當輸入6.660156M Hz的正弦波時，訊號對雜訊及失真比（SNDR）以及有效位元數（ENOB）的模擬結果分別為71.78 dB以及11.63，而平均功耗則為3.62mW，靜態分析DNL及INL的模擬結果分別為（1.004 / -1 LSB）以及（0.756 / -1.007 LSB）。

This thesis describes an analog-to-digital converter (ADC) for FHD image sensors. The ADC specification is 12-bit resolution and the sampling rate is 20 MHz. The architecture of this ADC is two-step successive approximation register (SAR) ADC. The disadvantage of the traditional SAR ADC is the great area of capacitor. When we add every 1-bit resolution, the area of the capacitor will double. In this thesis, the number of unit capacitor of the two-step SAR ADC is reduced to 1/16th of that of a conventional 12-b SAR ADC.
The prototype was fabricated using TSMC 0.18um 1P6M CMOS technology. At a 1.8-V supply and 20-M Hz sampling rate, simulations showed that the ADC achieves a SNDR of 71.78dB, an ENOB of 11.63 and power consumes 3.62mW.
The chip area including I/O pad is 1.109mm2 .The simulating results of static analysis DNL and INL are （1.004 / -1 LSB） and （0.756 / -1.007 LSB）.
Measurements showed that the chip layout might not be symmetric enough and it might degrade the ADC performance.

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