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研究生： 陳信勳
Chen, Shin-Shiun
論文名稱： Advanced Memory-Processor Stacking Architecture for High Performance and Low Power
高效能及低功耗之先進記憶體與處理器堆疊架構
指導教授： 吳誠文
Wu, Cheng-Wen
口試委員: 蘇朝琴
周世傑
黃錫瑜
吳誠文
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 中文
論文頁數： 58
中文關鍵詞： 三維堆疊 、動態隨機存取記憶體 、介面 、架構 、電子化系統層級
外文關鍵詞： 3-D Stacking, DRAM, Interface, Architecture, ESL
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    • 在這篇論文中，我們利用電子化系統層級 (ESL) 的方法以及模擬，在架構層級提出了一個基於矽穿孔 (Through Silicon Via, TSV) 三維堆疊技術的處理器及記憶體堆疊架構。我們的架構移除了傳統的快取記憶體，因此不僅可以減少成本並且可以減少能量消耗，非常適合重視功率消耗的嵌入式系統以及手持式裝置。我們利用了矽穿孔技術所提供的大量輸出入頻寬，加上因為三維堆疊技術而改善的處理器跟記憶體之間的速度差距, 讓我們可以藉由重新設計三維堆疊動態存取記憶體(DRAM)的內部架構以及介面協定，來達到簡化記憶體控制器以及減少更多能源及成本消耗的目的。

    我們使用現有商用之DRAM來建構出我們的時間以及功率的模型以利我們做架構驗證。功率部分我們利用DDR2來當作參考模型，時間的部分我們則利用Fast-Cycle RAM (FCRAM) 來當作我們的參考模型。至於模擬整體系統的行為我們則利用ESL方法所建構的虛擬平台，另外加上cycle-accurate的處理器模型來進行我們的架構分析以及驗證。從實驗結果可以發現，我們所提出來的架構對比於原來的2D設計，系統效能可以提升23.5%，但是能源的消耗量卻只有原來的20%。

    1 Introduction 1.1 Motivation 1.2 Three Dimensional (3-D) Integration Technology 1.2.1 Wire Bonding Technique 1.2.2 Micro-Bump Technique 1.2.3 Through Silicon Via (TSV) 1.3 Modern DRAM Architecture 1.3.1 Commodity DRAM 1.3.2 Fast-Cycle RAM (FCRAM) 1.3.3 Reduced-Latency DRAM (RLDRAM) 1.4 DRAM-Processor-Stacked Architecture 1.5 Electronic System Level (ESL) Technique 1.6 Thesis Organization 2 Architecture Evaluation 2.1 PAC Duo SOC 2.2 System Analysis 2.2.1 2-D Version 2.2.2 3-D Version 2.3 Simulation Schemes with Virtual Platform 2.3.1 TSV Channel Modeling 2.3.2 DRAM Modeling 3 Stacked-DRAM Architecture 3.1 Sans-Cache DRAM Architecture 3.1.1 Eliminate Address Multiplexing 3.1.2 Small Active Row Size 3.1.3 Wide I/O Design 3.1.4 A Scheme without DDR 3.1.5 Auto-Precharging Scheme 3.2 Timing Model 3.3 Power Model 3.3.1 DDR2 Current Profiles 3.3.2 Power Model of SCDRAM 4 Experimental Results 4.1 Experiment Environment 4.2 Architecture Comparisons 4.3 Benchmark Comparisons 4.4 Discussion 5 Conclusions and Future Work 5.1 Conclusions 5.2 Future Work 5.2.1 Memory Controller Design for SCDRAM 5.2.2 Many-Core System

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