隨著半導體技術持續發展，元件尺寸及金屬連線的間距皆被微縮以實現電路面積，速度之改善。當金屬連線的間距微縮，其所伴隨的寄生電阻、電容亦持續增加，因而增加金屬連線傳遞的時間延遲，此時間延遲已經成為電路設計的瓶頸之一。為了改善傳遞時間延遲的效應，採用銅導線及低介電材料已為不可避免的趨勢。雖然銅及低介電材料的技術可以有效地降低時間延遲效應，其低介電材料的時依性介電層崩潰現象卻成為低介電材料之可靠度問題。
本篇論文討論數種低介電材料之時依性介電層崩潰模型，發現金屬連線之漏電流傳輸機制對於時依性介電層崩潰現象扮演著重要的角色，因此對於數種低介電材料的潛在性傳輸機制做進一步探討，其中包含蕭基發射式電流模型(Schottky emission current model)、普爾-夫倫克爾發射式電流模型(Poole-Frenkel emission current model)及傅勒-諾德翰穿隧電流模型(Fowler-Nordheim tunneling current model)。這些潛在的漏電流傳輸機制已被實現於名為”kappa”的金屬連線模擬軟體，其模擬結果可以與實際量測互相比較。
本篇論文所探討的銅/極低介電常數材料金屬連線之測試結構是由台灣積體電路公司所製作。分別在三個不同溫度下進行電流-電壓量測以進行漏電流之探討。藉由比較量測數據與模擬結果兩者之斜率，其結果顯是銅/極低介電常數材料之漏電傳導機制是由蕭基發射式電流模型所主導，且銅及極低介電常數材料之介面能障高度為0.87eV。藉由此組模型參數，量測數據與模擬結果兩者有著相當好的匹配結果。
此外，藉由此組模型參數，我們也發現金屬連線對於漏電流最為敏感的參數為金屬連線之間距及介電材料之介電常數。較小的間距使得漏電流的增加，而較小的介電常數亦增加漏電流。由於製程技術之發展朝著微縮方向持續演進，可預期金屬連線之漏電流將越來越嚴重，此意味著時依介電崩潰現象亦越來越嚴重。

As the semiconductor technology development continues, device and interconnect line spacing are scaling down for achieving density and speed improvements. As the spacing is shrinking, it is accompanied by larger parasitic resistance and capacitance and hence larger interconnect delay. This interconnect delay has become one of the bottleneck for circuit design. In order to reduce interconnect delay, the use of Cu metallization and low-k dielectrics are required. Although Cu/low-k interconnect technology can effectively reduce RC delay, time dependent dielectric breakdown (TDDB) phenomenon of low-k material has become an important reliability issue.
In this thesis, several low-k TDDB models are reviewed and it is observed that the conduction mechanism of leakage current plays an important role in low-k TDDB phenomenon. Therefore, several leakage current models for low-k material are investigated. These include Schottky emission current model, Poole-Frenkel emission current model and Fowler-Nordheim tunneling current model. These leakage current models have been implemented in an interconnect simulation program, kappa, and can be compared to real silicon measurements.
Some Cu/ELK interconnect test structures have been fabricated by TSMC. I-V measurements are carried out to assess the leakage current, including at three different temperatures. By comparing the slopes of the I-V curves, obtained from measurement and simulations, it shows that the Schottky emission current model has the best match with the measurement results. The barrier height between copper and ELK is found to be 0.87eV. Using one set of model parameters, we can get excellent matches between simulation and measurement data.
Using this set of model coefficients, we also find that the most sensitive parameters of the leakage current are the line-to-line spacing and the ELK dielectric constant. Smaller spacing increases leakage current; while smaller dielectric constant also increases leakage current. Since this is the direction of technology scaling, it can be predicted that interconnect leakage current is getting more severe with scaling, so is the TDDB issue.

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