隨著超大型積體電路 (VLSI) 的演進，後段製程的金屬連接線 (Interconnect)
的尺寸也一直隨著製程技術的進步再縮小， 這樣的趨勢正好符合了晶片設計者
的需求，他們需要在更小的晶圓面積上面，擺上更多的電晶體，因此後段的金屬
連接線也就需要更加的縮小且更加的複雜。但是在製程的發展，當尺寸不停縮小
之後，在先前製程科技所不需要處理的效應，會因為製程科技的演進而浮現出
來。因此需要跟準確的後段製程的corner 模型來幫助設計者進行電路的設計。
在這一篇論文當中，我們設計了一個自動產生測試結構的產生器，產生器中
有內建了數種具有不同目的的P-cell，使用者可以針對自己的需求和目的來決定
產生出那些自己所需要的測試結構還有其大小，且可以客制化使用者的需求，利
用短暫的時間產生出使用者所需要的測試結構。這一個產生器可以針對超大型積
體電路的後段製程產生所需要的測試結構，在產生出測試結構之後，還會有進一
步的除錯動作，這個步驟可以針對大部分連接錯誤的問題作基本的除錯，並且利
用這些測試結構的測量值來推得SIPPs 參數。這些SIPPs 參數，便可以使用來建
立成為後段金屬連接線的corner 模型。

With the improvement of VLSI technology, dimensions of BEoL
(Back End of the Line) interconnect becomes smaller and smaller. For
most circuit designers, they want to put more transistors on the smaller
die size. Thus, interconnect will be complicated and scale down. There
are more interconnect-induced effects which need to be considered in
advanced technology when the process scales down. IC designers need an
accurate BEoL corner model to help their circuit design.
In this paper, we design a test structure generator. Inside the
generator, there are several P-cells for different purposes. They are
embedded test structures of the generator. Users can generate the test
structures by their requests. It can customize the requests from users.
Users only spend a short time and they can get their test structures. It
focuses on generating the test structures for VLSI BEoL. After the
generation of the test structures, there is still a step for debug. This step
can find most connectivity errors. Using these structures to measure all
electronic data can derive to get SIPPs, which are the parameters for
VLSI BEoL corner model.

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