本文針對微波頻段的無線-有線通訊系統提出了二個創新的技巧用於增加CMOS積體電路放大器的效能。我們將這二個方法分別展示在一個窄頻放大器和一個寬頻放大器中，且這第二個放大器都使用了標準的0.18-μm RF CMOS製程。與使用相同或更先進製程的文獻相比，這二個放大器的效能皆優於或可與其相提並論。
所設計的窄頻放大器為操作在24 GHz、增益為45 dB的平衡式放大器(Balanced amplifier, BA)。此放大器使用了本文所提出的窄頻電路技術：π型並聯共振器(π-type parallel resonance, PPR)。藉由共振掉電晶體天生的寄生電容，PPR可有效的增加電晶體的高頻增益。在耦合器的設計方面，我們使用了微小式的集總元件耦合器因為此面積只有傳統的傳輸線耦合器的2 %。所設計的BA特性為：操作電壓1 V、消耗功率123 mW、增益45 dB、晶片面積0.97 × 0.63 mm2、主要電路面積0.78 × 0.43 mm2。跟其它使用相同製程和操作頻率的窄頻放大器所比，此放大器的增益為最高。
所設計的寬頻放大器為40-Gb/s的轉阻放大器(Transimpedance amplifier, TIA)。此放大器使用了本文所提出的寬頻電路技巧：π型電感式peaking (π-type inductor peaking, PIP)。對一個共源級放大器而言，PIP可增加頻寬達3.31倍。另外，PIP用於輸入級也可使得雜訊電流隨著頻率增加而減少。所設計的TIA特性為：操作電壓1.8 V、消耗功率60.1 mW、轉阻增益51 dBΩ、頻寬30.5 GHz、晶片面積1.17 × 0.46 mm2、增益頻寬積除以直流功率180.1 GHzΩ/mW。

This study proposed new circuit design techniques to achieve high-performance CMOS integrated amplifiers for wireless/line communications at microwave frequencies. The design concepts were demonstrated by one narrowband and one broadband amplifiers, which were both realized in the standard 0.18-μm RF CMOS technology. The measured results presented superior performances compared with other published works using a similar or even more advanced CMOS technology.
The designed narrowband amplifier is a 24-GHz balanced amplifier (BA) with a gain up to 45 dB. An effective technique, π–type parallel resonance (PPR), was proposed to boost the high frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~ 2 % compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. The proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 × 0.63 mm2 (core area: 0.78 × 0.43 mm2) among the published narrowband amplifiers with similar technologies and operation frequencies.
The designed broadband amplifier is a 40-Gb/s transimpedance amplifier (TIA). From the measured S-parameters, a transimpedance gain of 51 dBΩ and a 3-dB bandwidth up to 30.5 GHz were observed. A gain-bandwidth product (GBW) enhancement technique, π-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 × 0.46 mm2. The proposed CMOS TIA presents a GBW per DC power figure-of-merit (GBP/Pdc) of 180.1 GHzΩ/mW.

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