由於浮動式閘極快閃記憶體無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體式取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽做為電荷儲存層的結構，在發展到次微米以下時就無法再以降低穿隧氧化層厚度的方式來提升元件操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作機制。而在通道介面處磊晶一層矽化鍺，藉由能帶工程提升操作載子的能量，希望藉此材料的應用達到較高的元件操作效率。
本論文的研究方向主要分為下列三項：
(1) 藉由改變矽化鍺通道的鍺含量，來調變矽化鍺通道介面處的能隙，改變穿隧載子的穿隧能量，來比較不同條件對於元件操作效率上的改善。
(2) 藉由改變矽化鍺通道的厚度，以及堆疊方式，來調變矽化鍺通道介面處的穿隧範圍以及對於單晶矽覆蓋層的應力問題，來比較不同條件對於元件操作效率上有什麼影響。
(3) 改變矽化鍺通道上方的單晶矽覆蓋層厚度，藉此改善矽化鍺通道與穿隧氧化層之間的介面特性，觀察用此方式對於元件電性上有改善與影響。
而經由實驗結果發現，引進矽化鍺通道的記憶體元件，相較於傳統矽基板在操作效率上有明顯的提升，並發現在固定單晶矽覆蓋層厚度前提下，鍺含量越低，以及矽化鍺通道厚度越薄，元件操作效率會越來越好，而改變單晶矽覆蓋層厚度以求改進介面特性部份，隨著單晶矽覆蓋層厚度增加，元件操作效率也會有隨之變好的趨勢。

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