在三維晶片的相關研究中，矽晶穿孔的可靠性逐漸地變得愈來愈重要，由於矽晶穿孔的損壞機率愈高愈易造成更多的晶片無法使用。因此，在先期的研究中提出了一個新的矽晶穿孔容錯設計，它增強了三維晶片時脈樹對矽晶穿孔的容錯。然而此矽晶穿孔容錯設計中所增添的延遲緩衝器可能產生大量的功率消耗。
在這篇論文中，我們提出了兩種方法來解決矽晶穿孔容錯設計中延遲緩衝器對晶片造成的負擔。第一種方法，藉由分析時脈訊號的延遲，運用線性規劃來重新調整延遲緩衝器的大小。第二種方法，在晶穿孔容錯設計中插入橫跨兩子樹的導線(crosslink)，進一步的降低延遲緩衝器的大小並對電路提供抗變化的能力。實驗數據顯示，我們的方法相對於先期的研究，確實能有效降低電路功率的消耗且更能抗變化。

The reliability of through-silicon via (TSV) is becoming increasingly important in 3D ICs. Since the higher failure rate of TSV in clock tree yields more bad chips. Accordingly, the previous work proposes a novel TSV fault-tolerant unit (TFU), which can provide tolerance against TSV failure in a 3D clock network. However, the TFU structure’s additional buffers could take considerable power consumption. Also, the TFU structure
In this thesis, we present two methodologies to resolve the TFU delay buffer overhead. (1) Analyze clock signal delay and resize the TFU’s delay buffers by linear programming. (2) Insert crosslink in TFU to achieve further buffer sizing and provide variation tolerance. Experimental results demonstrate that our methodologies make the circuit have lower power consumption and better variation tolerance compared with the previous work.

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