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研究生: 陳昭男
Jau-Nan Chen
論文名稱: High-k應用於SONOS快閃記憶體電荷儲存層之研究
A study of SONOS-Type Flash Memory Using High-k Charge Storage Layers
指導教授: 李雅明
Ya-Min Lee
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 94
中文關鍵詞: 非揮性記憶體氧化鉿氧化鋯
外文關鍵詞: SONOS, MOHOS, MOZOS
相關次數: 點閱:3下載:0
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  • 中 文 摘 要

    我們已經研究金屬-氧化物-高介電係數介電層-氧化物-矽結構(SONOS-Type Flash Memory) 並使用HfO2 and ZrO2 作為高介電係數介電層結構的電容器和電晶體,分別稱作MOHOS與MOZOS。並對元件作基本的電性量測與可靠度分析;首先藉由不同的儲存層材料的差異,探討其對SONOS元件電特性的影響;再來探討不同RTA溫度對儲存層特性的影響。
    Memory window方面,電容器結構在用as-deposited 的ZrO2所得到的Memory Window為7V是最大的情況,並計算出電荷密度為5.3×1013cm-2,且電荷保持力(retention time) 在十年後仍有0.5V的門檻電壓差。N-channel MOHOS電晶體,我們使用射頻磁控濺鍍法沈積HfO2或ZrO2薄膜,結果得到用as-deposited的high-k薄膜作儲存層時,memory window、寫入抹除速度和電荷保持力皆比其它情況好。
    在基本電性上的表現,如:ID-VD,ID-VG及C-V等,皆證明電晶體能夠正常的操作,且發現臨界電壓約在1.9V,最小的次臨界斜率是85.5 mV/dec.,在VD=0.05V下,ION/IOFF的比例有5個數量級之多。經由次臨界斜率St=2.3(kT/q)[1+(CD+Cit)/Cox]的計算,可以得到界面缺陷電荷密度(Dit)為5.73x1011 cm-2-eV-1。


    第一章 緒論---------------------------------------------------------------------------1 1.1前言-----------------------------------------------------------------------------------1 1.2非揮發性記憶體的演化過程-----------------------------------------------------1 1.3研究動機-----------------------------------------------------------------------------4 第二章 快閃記憶體的可靠度問題之探討---------------------------------5 2.1寫入機制比較-----------------------------------------------------------------------5 2.2擦拭機制比較-----------------------------------------------------------------------6 2.3電荷保持力--------------------------------------------------------------------------7 2.4 耐久度-------------------------------------------------------------------------------8 2.5干擾-----------------------------------------------------------------------------------9 2.6過度擦拭-----------------------------------------------------------------------------9 2.7結論----------------------------------------------------------------------------------10 第三章 MOHOS和MOZOS記憶體元件的製備---------------------11 3.1射頻磁控濺鍍法(RF magnetron sputtering)的簡介----------------------11 3.2歐姆接面(Ohmic contact)的製備---------------------------------------------12 3.3 OHO和OZO薄膜的成長--------------------------------------------------------12 3.4 MOHOS和MOZOS薄膜電容器的製備--------------------------------------13 3.5 MOHOS和MOZOS薄膜電晶體的製備--------------------------------------13 3.6 蝕刻上遭遇到的問題------------------------------------------------------------16 第四章 MOHOS和MOZOS電容器電流機制探討------------------17 4.1單層漏電流傳導機制之簡介----------------------------------------------------17 4.1.1 蕭基發射(Schottky emission)------------------------------------------18 4.1.2 普爾-法蘭克發射(Poole-Frenkel emission)-------------------------18 4.1.3 佛勒-諾德翰穿隧(Fowler-Nordheim tunneling)------------------19 4.2多層漏電流傳導機制之簡介----------------------------------------------------20 4.3 OHO三層結構電容器之漏電流傳導機制分析------------------------------20 4.3.1 OHO三層Fowler-Nordheim tunneling fitting--------------------------20 4.3.2 OHO三層Modified-Fowler-Nordheim tunneling fitting-------------21 4.4 本章結論---------------------------------------------------------------------------22 第五章 不同製程對MOHOS與MOZOS電容元件電性之影響--------------------------------------------------------------------------------------------23 5.1 研究目的---------------------------------------------------------------------------23 5.2製程與量測方式-------------------------------------------------------------------23 5.3實驗結果與討論-------------------------------------------------------------------24 5.3.1不同high-k材料及不同RTA溫度對C-V memory window大小的影響--------------------------------------------------------------------------------24 5.4 MOHOS薄膜物性分析---------------------------------------------------------26 5.4. 1二次離子質譜儀縱深分佈之分析--------------------------------------26 5.4. 2 X-ray 繞射分析------------------------------------------------------------27 5.5 結論---------------------------------------------------------------------------------27 第六章 MOHOS和MOZOS記憶體元件的製備---------------------29 6.1研究目的----------------------------------------------------------------------------29 6.2製程與量測方式-------------------------------------------------------------------29 6.3實驗結果與討論-------------------------------------------------------------------30 6.4電晶體基本電性量測-------------------------------------------------------------31 6.4.1 IDS-VDS 曲線的特性探討------------------------------------------------32 6.4.2 次臨界斜率 (subthreshold swing)-------------------------------------32 6.4.3 臨界電壓 (threshold voltage) 的粹取--------------------------------33 6.4.4 遷移率 (mobility) 的探討----------------------------------------------33 6.5結論----------------------------------------------------------------------------------34 第七章 結論-------------------------------------------------------------------------35 Reference-----------------------------------------------------------------------------36 實驗圖表------------------------------------------------------------------------------39 附錄-------------------------------------------------------------------------------------89 1. 射頻磁控濺鍍法操作步驟 2. 電晶體製程之三道光罩圖

    [1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, pp.1288, 1967.
    [2] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable MOS-ROM,” IEEE ISSCC Dig. Tech. Pap., pp. 80, 1971.
    [3] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R.E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” in IEDM Tech. Dig., 1967.
    [4] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S.H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in IEDM Tech. Dig., pp. 32.6.1 -32.6.4., 2001.
    [5] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakaca, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-K charge trapping layer,” 2003 IEEE Symposium on VLSI Technology Digest of Technical, pp. 24-28.
    [6] C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, “An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase,” in IEDM Tech. Dig., pp. 927-930, 2002.
    [7] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett., vol. 68, no. 10, pp. 4, 1996.
    [8] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: Device Design and Fabrication,” IEEE Transactions on Electron Devices, vol. 49, no. 9, 2002.
    [9] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, ”Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer,” IEEE Transactions on Electron Devices, vol. 51, no. 7, 2004.
    [10] B. Jiankang and M. H. White, “Design considerations in scaled SONOS nonvolatile memory devices,” Solid State Electron., vol. 45, pp. 113–120, 2001.
    [11] H. Wann and C. Hu, “High endurance ultrathin tunnel oxide in MONOS device structure for dynamic memory applications,” IEEE Electron Device Lett., vol. 16, pp. 491–493, 1995.
    [12] Y. Kamagaki, S. I. Minami, T. Hagiwara, K. Furusawa, T. Furuno, K. Uchida, M. Terasawa, and K. Yamazaki, “Yield and reliability of MNOS EEPROM products,” IEEE J. Solid-State Circuits, vol. 24, pp. 1714–1722, 1989.
    [13] M. H. White, D. A. Adams, and B. Jiankang, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, pp. 22–31, 2000.
    [14] W. D. Brown and J. E. Brewer, Eds., Nonvolatile Semiconductor Memory Technology, A Comprehensive Guide To Understanding and Using NVSM Devices. New York: IEEE Press, pp. 193–309, 1998.
    [15] Yamada, Y. Hiwa, T. Tamane, K. Amemiya, Y. Ohshima, and K. Yoshikawa, ”Degradation Mechanism of Flash EEPROM Program After Program/Erase Cycles”, in IEDM Tech. Dig., pp. 23, 1993.
    [16] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S. H. Gu, ”Data retention behavior of a SONOS type two-bit storage flash memory cell”, in IEDM Tech. Dig., pp. 32.6.1-32.6.4., 2001.
    [17] B. Jiankangand and M. H. White, “Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices”, IEEE Electron Device Lett., vol. 22, no. 1, pp. 17 -19, 2001.
    [18] S. M. Sze, Physics of Semiconductor Device, 2nd ed., Wiley, New York, 1981.
    [19] J. R. Yeargan and H. L. Taylor, “The Poole-Frenkel Effect with Compensation Present,” J. Appl. Phys. vol. 39, no. 12, pp. 5600-5604 , 1968.
    [20] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/hafnium oxide/silicon structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, 2002.
    [21] D.K. Schroder, “Semiconductor material and device characteristics,” Wiley, Arizona, 1998.
    [22] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969.
    [23] B. Hankang and M. H. While, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” Aerospace Conference Proceedings, 2002. IEEE., vol, 5, pp. 2383-2390, 2002.
    [24] M. French, H. Sathianathan, and M. White, “A SONOS Nonvolatile Memory Cell For Semiconductor Disk Application,” Nonvolatile Memory Technology Review, 1993, pp. 70-73, 22-24, 1993.
    [25] M. Balog, M. Schieber, M. Michman, and S. Patai, “Chemical vapor deposition and characterization of HfO2 films from Organo-Hafnium compounds,” Thin Solid Films, vol. 41, pp. 247- 259, 1997.
    [26] C. H. Choi, T. S. Jeon, R. Clark, and D. L. Kwong, “Electrical properties and thermal stability of HfxOy gate dielectric with poly-Si gate electrode,” IEEE Electron Device Lett., vol. 24, pp. 215-217, 2003.
    [27] K. Nomoto, I. Fujiwara, H. Aozasa, T. Terano, and T. Kobayashi, “Analytical model of the programming characteristics of scaled MONOS memories with a variety of trap densities and a proposal of a trap-density-modulated MONS memory,” in IEDM Tech. Dig., pp. 13.5.1-13.5.4, 2001.
    [28] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, no. 11, pp. 9298-9300, 2003.

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