電阻式記憶體元件由於製程容易、結構簡單以及卓越的性能表現，在近年來受到廣大的矚目，並渴望成為下一世代非揮發性記憶體發展的主流之一。電阻式記憶體阻值轉換主要是由燈絲傳導路徑的形成與斷裂所產生。然而，在絕緣層中燈絲傳導路徑將會隨機形成，使元件阻轉轉換行為較不穩定。因此，如何有效控制燈絲的形成，使阻值轉換表現穩定，便成為電阻式記憶體元件研究的課題。
本實驗藉由插入不同厚度的銅於氧化鎂絕緣層內，試圖改善元件阻值轉換表現。跟不含銅的氧化鎂元件相比，當插入厚度5nm的銅，其電性表現仍然具有非極性操作的優勢。並且，在阻值轉換上不需要經過初始化過程。除此之外，阻值轉換時工作電壓分佈較具一致性，操作能量也大幅下降許多。經由電性分析，元件阻值轉換主要是由燈絲傳導路徑的形成與斷裂所導致，結合SIMS縱深分佈、XPS分析與變溫量測的結果，推測燈絲傳導路徑主要是由金屬鎂與一小部份的金屬銅所組成。利用TEM分析，可以發現5nm厚度的銅插入在絕緣層內，將會結成球狀，形成銅奈米晶體。由於銅奈米晶體的產生，在外加電場時，這些區域會造成電場集中，提供燈絲傳導路徑一個簡易的生成位置，藉由控制燈絲路徑的生
成位置，元件能夠具有較穩定的阻值轉換行為。最後藉由電性傳導機制的探討，在高阻態時漏電流傳導，跟不含銅的氧化鎂元件相比，電子傳導會從Schottky emission轉換形成Poole-Frenkel emission，由於銅在絕緣層內部將成為電子補陷中心的位置，因此，電子躍遷只需較少的能量即可激發至絕緣層的導帶，導致阻值轉換產生時所需的等效電場大幅下降。

In this paper, the resistive switching characteristics of MgO-based with a thin Cu insertion layer are reported in the Pt/MgO/Pt memory devices by ion beam deposition. With fixed thickness of dielectric layer sandwiched in Pt electrodes, we alter the thickness of the copper insertion and select the best electrical properties among them. It is found that besides the distinct reduction in memory switching parameters in SET and RESET voltages, an improvement in the stability of their dispersions were also achieved. The effects of Cu insertion layer on improving the resistive switching properties are analyzed by electrical measurements, Secondary Ion Mass Spectroscopy (SIMS), X-ray photoelectron spectroscopy (XPS), temperature dependence of resistance, and transmission electron microscopy (TEM). Additionally, on the comparison of switching mechanism in the MgO memory device with and without Cu nanocrystal embedded, the dominating conduction mechanism in low resistance state between them is the same; however, the dominating conduction mechanism in high resistance state is Poole-Frenkel emission and shottky emission, respectively, consisting with Cu atoms as defect trapping sites.

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