利用時脈數精準的交易層級塑模進行快且準的多核心單晶片系統模擬

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研究生：	羅振綱
論文名稱：	利用時脈數精準的交易層級塑模進行快且準的多核心單晶片系統模擬 Cycle-Count-Accurate Transaction-Level Modeling for Efficient Precise MPSoC Simulation
指導教授：	蔡仁松
口試委員:	林永隆許雅三陳添福劉靖家黃鍾揚
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2012
畢業學年度：	101
語文別：	英文
論文頁數：	56
中文關鍵詞：	單晶片系統設計、交易層級模型、系統效能分析、電子系統設計
相關次數：	點閱：4 下載：0
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因應持續上升的單晶片系統複雜度，如何良好得進行早期驗證變成系統設計的成敗關鍵。因此，邁向更高的抽象層級，交易層級模型被提出來支援早期系統設計及驗證。尤其是多處理器單晶片，由於設計上有很多軟硬體並行的運行行為，造成其架構或者功能驗證更加複雜。理想上，應該要能夠建構交易層級模型以提供快速且精確的模擬，來支援多處理器單晶片系統的架構及功能驗證。然而，現行的時脈精準(Cycle Accurate)塑模方法由於保留過多設計細節，所以模擬速度緩慢；另一方面，時脈近似(Cycle Approximate)塑模方法由於過度簡化而不精準。為了達成快且準的模擬，這篇論文探討如何建構時脈數精準模型(Cycle Count Accurate)。我們在這篇論文中提出第一個系統化的方法建構時脈數精準的亂序匯流排模型，以及第一個時脈數精準處理器模型。實驗結果顯示，用我們提出的塑模方法，其時脈數精準匯流排模型可以比其時脈精準模型模擬速度快12倍，而時脈數精準處理器模型可以快50倍；同時我們的時脈精準數模型可以得到跟傳統時脈精準模型一樣的模擬運行結果。因此，我們的方法可以達成快且準的系統模擬以支持其架構及功能驗證。

Chapter 1.    Introduction    6
1.    The TLM-based Design Methodologies    6
2.    The Deficiency of Existing TLM Models    8
3.    Our Proposed Cycle-Count-Accurate Models    9
Chapter 2.    CCA Modeling of Out-of-order Pipelined Buses    10
1.    Introduction    10
1.1.    Chapter overview    10
1.2.    Related Work    12
2.    Cycle-level Formal Description    14
2.1.    Formal NP Bus Modeling    14
2.2.    Generic PL/OO Bus Modeling    17
3.    Static Transaction Abstraction    20
3.1.    The Abstraction Idea    21
3.2.    Transaction Abstraction    22
3.3.    Discussions    25
4.    TLM Simulation Model Generation    27
4.1.    Conversion to Event-Driven Arbitration Model    27
4.2.    Automatic Bus Model Generation    30
5.    Experiments    31
5.1.    Modeling and Simulation of Bus Matrix of PAC-Octal Platform    31
5.2.    Architecture Performance Evaluation    34
6.    Summary    36
Chapter 3.    Cycle-Count-Accurate Processor Modeling    37
1.    Introduction    37
1.1.    Chapter overview    37
1.2.    Related Work    38
2.    Cycle Count Accurate Processor Modeling    40
3.    Pipeline Subsystem Modeling (PSM)    42
3.1.    Static Timing Analysis    42
3.2.    Dynamic Timing Calculation    45
3.3.    Discussions    45
4.    Cache Subsystem Model (CSM)    46
5.    A Case Study    47
5.1.    OR1200 CCA Processor Modeling    47
5.2.    Experimental Results    48
6.    Summary    49
Chapter 4.    Conclusion and Future Work    50
REFERENCES    51
APPENDIX A    54
APPENDIX B    56


                                

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