積體電路中，時脈訊號是同步設計中共同的參考時間點。時脈散佈網路的設計會直接影響整個晶片的效能，例如時脈偏差以及耗能。本論文建立了一套快速的電源/地線雜訊模擬演算法，接著探討時脈訊號的議題中兩種節能方法，並且提出兩種結構設計用以解決其問題。
首先，我們提出了一個基於向量梯度法的電壓差模擬演算法。一般普遍認為向量梯度法適合解決大型但鬆散的對稱正定線性系統。使用向量梯度法的一個關鍵問題在於設計一個適合的預處理子。適合的預處理子可以大幅的節省計算時間並且有效率的使用記憶體。通用的預處理子通常非常容易尋找，但效果則是隨著不同問題而起伏。另一方面，針對問題而特別設計的預處理子通常效果良好但是非常難以設計。這個部分我們研究了「電源網格模擬競賽」的問題，並且根據電源網格設計了一個新的預處理子。實驗結果顯示比起通用預處理子，此預處理子可以讓收斂迴圈減少43%並且讓執行時間減少23%。
接著，我們討論了節能議題。在高效能的設計中，共振時脈被用來實現能源回收。但是共振時脈需要額外加入去耦電容，造成相當大的面積負擔。為了克服共振時脈的面積問題，我們提出一個新的共振時脈設計，稱作乒乓網格。乒乓網格包含兩個子網格，每個子網格互相扮演對方的去耦電容，兩個子網格的時脈運作完全反向。因此，比起傳統的共振時脈，乒乓網格不需要額外加入去耦電容。並且，比起傳統的共振時脈，乒乓網格可以減少大約一半的瞬間最大電流。
最後，多重電壓模式設計是另外一個相當實用的節能方法，並且不會犧牲晶片的效能。然而當運作電壓下降至超低壓等級時，不同電壓模式之間會出現相當大的時脈偏差。若使用傳統的「考慮電壓模式緩衝器」來消弭時脈偏差，會需要加入大量的緩衝器並且造成相當大的功率消耗。這個部分我們提出一個新的「考慮電壓模式緩衝器」架構，同時可以節能並且消除時脈偏差。我們提出的「考慮電壓模式緩衝器」包含兩個串聯的子緩衝器分別運作在不同電壓下：前端的子緩衝器運作在低電壓，用以初步消弭大量的時脈偏差；接著，後端的子緩衝器運作於高電壓，用以消弭較細的時脈偏差。

Clock signal is the common timing reference for all synchronous sequential components in integrated circuits. The design of clock distribution network can affect a chip’s performance directly such as clock skew and power consumption. In the beginning of this dissertation, we build a fast power /ground noise simulation environment. After that, we aim to the clock design issues of two different low power techniques, and propose two architectures to resolve the problem respectively.
First, we propose an IR drop simulation algorithm in this dissertation based on Preconditioned Conjugate Gradient (PCG) method. PCG has been demonstrated to be effective in solving large-scale linear systems for sparse and symmetric positive definite matrices. One critical problem in PCG is to design a good preconditioner, which can significantly reduce the runtime while keeping memory usage efficient. Universal preconditioners are simple and easy to construct, but their effectiveness is highly problem-dependent. On the other hand, domain-specific preconditioners that explore the underlying physical meaning of the matrices usually work better, but are difficult to design. In this part, we study the problem in the context of power grid simulation, and develop a novel preconditioner based on the power grid structure through simple circuit simulations. Experimental results show 43% reduction in the number of iterations and 23% speedup over existing universal preconditioners.
After that, we focus on the low-power issues. Resonant clock has proposed for energy recycling in high-performance design. However, the resonant clock often suffer from area overhead because of the need to insert large decoupling capacitors. To overcome the area overhead for resonant clock, we propose a novel resonant clock mesh structure, called Ping-Pong mesh. Ping-Pong mesh contains two sub-meshes, each of which plays the role of the decoupling capacitor of the other, and the clocks in two sub-meshes operate in completely opposite phases. As the result, a Ping-Pong mesh does not need additional decoupling capacitors as in previous works. Also, Ping-Pong mesh can reduce the power-ground surge current about half of previous works.
Finally, multi-power-mode design is another useful technique for lowing the chip power without sacrificing circuit speed. However, as the supply voltage is down to the ultra-low voltage level, a huge clock skew may occur among different power modes. If conventional power-mode-aware buffers (PMABs) are used to eliminate the clock skew, a large overhead on power consumption will be introduced. In this section, we propose a new PMAB architecture to save the power consumption for clock skew minimization. The proposed PMAB architecture is composed of two serially-connected sub-PMABs at two different voltage levels, respectively: in the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization; then, in the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization.

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