研究生: |
胡喻評 Yu-Ping Hu |
---|---|
論文名稱: |
金屬/鐵電層/絕緣層/矽 結構電容之試製與電性分析 The electrical properties of metal-ferroelectric-insulator-silicon(MFIS) structures for non-volatile memory applications |
指導教授: |
李雅明
Ya-Min Lee |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2004 |
畢業學年度: | 92 |
語文別: | 中文 |
論文頁數: | 77 |
中文關鍵詞: | 鐵電材料 、鋯鈦酸鉛 |
外文關鍵詞: | ferroelectric, PZT, MFIS |
相關次數: | 點閱:3 下載:0 |
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本實驗以射頻磁控濺鍍法製備金屬-鐵電(鋯鈦酸鉛)-絕緣層-半導體電容。本實驗採用三種不同絕緣層(insulator) La2O3, HfO2以及Dy2O3,以射頻磁控濺鍍法方式,沉積不同厚度當作緩衝層(buffer layer)。而後經由不同溫度的熱退火處理後,再以射頻磁控濺鍍法沈積PZT,最後再以lift-off的方式製作上電極,由此完成樣品的製作。自發性極化的特性是鐵電材料應用於非發揮性記憶體的主要精神,故本實驗主要是藉由電容-電壓以及電流-電壓的量測探討鐵電材料在其中所扮演的角色。
在本實驗中我們成功的製作金屬/鐵電薄膜(PZT)/絕緣體(Dy2O3)/半導體(p-Si)電容器,並對其電性作分析,由電容-電壓的量測結果,我們可發現其C-V曲線走向在掃瞄振幅電壓小於8V時為順時針走向,而在掃瞄振幅電壓大於8V時為逆時針走向,這表示在當外加電壓小於8V時,C-V走向是鐵電極化在主導;當外加電壓大於8V時,電荷注入的影響大於鐵電極化,因此C-V走向是電荷注入在主導。關於矯頑電場與記憶窗之間的關係也針對文獻上的結果與本實驗所得之結果有進一步的探討與分析,結果顯示在振幅電壓在鐵電極化主導時,符合公式 □Vwindow=2dfEc ,因為當電壓大於8V後,C-V曲線將由電荷注入主宰而非鐵電極化來主宰。而在電流-電壓的量測中,我們利用能帶圖配合鐵電材料的特性,成功的解釋在不同偏壓下的漏電流現象;同時,由漏電流的等級在以Dy2O3為絕緣層的樣品(在10 V時,漏電流密度由室溫1x10-7 A/cm2到450 K漏電流密度2x10-2 A/cm2)可知絕緣層成功的扮演降低漏電流的角色。
The electrical characteristics of metal-ferroelectric-insulator-silicon (MFIS) structures are studied. The ferroelectric layer is lead-zirconate-titanate (PZT). High dielectric constant films of La2O3 , HfO2 and Dy2O3 are used as the insulator layer . This structure is studied for the potential application of non-volatile memory devices. The PZT and the high-κ dielectric films are deposited by RF magnetron sputtering. The orientation of C-V hysteresis loop is found to depend on both the polarization of the ferroelectric layer and the trapped charges injected into the insulator layer. For the Al/Pb(Zr0.6,Ti0.4)O3 (PZT)/ La2O3/Si structure , the memory window is agreement with the theoretical result of ΔV= 2dfEc (1.7 V) at an applied voltage of 5 V .The leakage current density is about 10-7 A/cm2 at room temperature and is about 4×10-5 A/cm2 at 425 K under the bias of 10 V . For the Al/PZT/Dy2O3/Si system, the C-V orientation is counterclockwise when the applied voltage is below 8 V and clockwise above 8 V. The memory window measured from the C-V curves first increases and then decreases with the applied sweep voltage. These phenomena are explained by the combination of the polarization of the ferroelectric film and the injected charge effects in the Al/PZT/Dy2O3/Si MFIS system .The leakage current density is about 9×10-7 A/cm2 at room temperature and rises to 5×10-2 A/cm2 at 450K under the bias of 10 V.
第一章
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第二章
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第三章
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第四章
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第五章
[1] M. Yamaguchi, K. Hiraki, T. Homma, T. Nagatomo, and Y. Masuda, “Fabrication and properties of Bi2SiO5 thin films for MFIS structures,” Proc. of 12th IEEE Int. Symp. On Application of Ferroelectrics, 2000, pp. 629-632.
[2] H. N. Lee, Y. T. Kim, C. W. Lee, and S. H. Choh, “Enhancement of memory window in the metal/ferroelectric (YMnO3 )/insulator/semiconductor capacitor,” Proc. of 11th IEEE Int. Symp. On Application of Ferroelectrics, 1998, pp. 39-42.