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研究生: 林建霖
Lin, Jian Lin
論文名稱: 垂直型溝槽式閘極氮化鎵金氧半場效電晶體之製作
The Fabrication of Vertical Trench Gate GaN MOSFETs
指導教授: 黃智方
Huang, Chih Fang
口試委員: 李坤彥
巫勇賢
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 67
中文關鍵詞: 氮化鎵垂直型溝槽式閘極金氧半場效電晶體
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  • 本篇論文使用在氮化鎵基板上以MBE成長之氮化鎵試片製作垂直型溝槽式閘極MOSFET,探討以ALD沉積不同閘極氧化層及歐姆接觸之快速熱退火製程對元件電性的影響。
    本次實驗之試片變因分別為: (A) 以80 nm Al2O3做為閘極氧化層並在氮氣環境下進行850°C 30秒之歐姆接觸快速熱退火。(B) 以80 nm Al2O3做為閘極氧化層但不經過快速熱退火。(C)以40 nm Al2O3/40 nm SiO2做為閘極氧化層且不經過快速熱退火。(D) 以40 nm SiO2/40 nm Al2O3做為閘極氧化層且不經過快速熱退火。
    元件製作完成後發現其中有大量的Trap,必須以Pulse模式量測並且在UV光的照射下才會有較合理的直流特性。由Sample A發現快速熱退火會降低元件的電流密度。由雙向ID-VG發現Sample C相對於Sample D有較大的遲滯。
    整體而言,由於Sample B的閘極氧化層使用80nm高介電系數的Al2O3並且未經高溫快速熱退火製程,因此有較好的元件順向特性,Vth為8.2 V,電流密度可達5 A/mm2,Ron,sp約為7.71 mΩ-cm2。而元件漏電流偏大,崩潰電壓只有約200 V左右。


    In this thesis, we fabricated vertical trench gate GaN MOSFETs on MBE grown epitaxial layers on GaN substrates, and investigated the effects on device characteristics from different ALD gate insulators and RTA process for ohmic contacts.
    The samples of this experiment included: (A) a 80 nm Al2O3 as the gate insulator with RTA at 850°C in N2 ambient for 30s for ohmic contact. (B) a 80 nm Al2O3 as the gate insulator without RTA. (C) a 40 nm Al2O3/40 nm SiO2 as the gate insulator without RTA.(D) a 40 nm SiO2/40 nm Al2O3 as the gate insulator without RTA.
    It was observed that there were a significant amount of traps introduced in the device after processing. These devices had to be measured by pulse mode and under UV light to show reasonable DC characteristics. It was also found that the current density was reduced by RTA from sample A. And from sweeping ID-VG in both directions, the hysteresis for sample C is larger than sample D.
    In general, Sample B shows better forward characteristics due to a 80nm high dielectric constant Al2O3 as the gate insulator and the elimination of high temperature RTA. The Vth is 8.2 V, the current density reaches 5 A/mm2, and the Ron,sp is about 7.71 mΩ-cm2. The breakdown voltage is about 200 V with a large leakage current.

    中文摘要 I Abstract II 目錄 III 圖目錄 V 表目錄 VIII 第一章 序論 1 1.1 前言 1 1.2 研究動機與文獻回顧 3 1.3 研究方向簡介與論文架構 10 1.3.1 研究方向簡介 10 1.3.2 論文架構 10 第二章 材料介紹與實驗設計 11 2.1 氮化鎵材料介紹與磊晶方式 11 2.2 試片磊晶結構 11 2.3 閘極氧化層比較 12 2.4 元件隔離方式 13 2.5 實驗設計 13 2.5.1 光罩設計 14 2.5.2 試片分類 15 第三章 光罩設計與元件製程 16 3.1 垂直型溝槽式閘極MOSFET元件製作流程 16 3.2 試片之溶劑清潔 17 3.3 蝕刻出對準記號與閘極溝槽 (Mask 1) 17 3.4 蝕刻出基極溝槽 (Mask 2) 19 3.5 表面處理與沉積閘極氧化層 21 3.6 蝕刻源極與基極之氧化層 (Mask 3) 22 3.7 蒸鍍源極與汲極電極 (Mask 3) 23 3.8 蒸鍍源極襯墊金屬 (Mask 4) 24 3.9 蒸鍍閘極金屬 (Mask 5) 24 3.10 蝕刻出元件隔離區 (Mask 6) 25 3.11 離子佈植使元件隔離 (Mask 7) 26 第四章 元件量測結果分析 28 4.1 TLM測試元件量測 28 4.2 電容CV量測 31 4.3 閘極氧化層崩潰特性 34 4.4 不同Isolation方式對元件漏電流之影響 36 4.5 元件正向電流-電壓特性量測 38 4.5.1 DC模式下之ID-VD量測 38 4.5.2 Pulse模式下之ID-VD量測 38 4.5.3 DC模式下照射UV光之ID-VD量測 38 4.5.4 Pulse模式下照射UV光之ID-VD量測 39 4.6 元件崩潰特性量測 54 4.7 升溫量測 57 第五章 結論與未來工作 64 參考文獻 65

    [1] N. Kaminski, “State of the art and the future of wide band-gap devices,” in Proc. IEEE Power Electron. Appl. pp. 1-9, 2009.
    [2] M. N. Yoder, “Wide bandgap semiconductor materials and devices,” IEEE Trans. Electron Devices, vol. 43, pp. 1633-1636, 1996.
    [3] B. J. Baliga, “Advanced Power MOSFET Concepts,” Springer Verlag, 2010.
    [4] ] B. Han, S. W. Lee, K. Park, C. O. Park, S. K. Rha, W. J. Lee, “The electrical properties of dielectric stacks of SiO2 and Al2O3 prepared by atomic layer deposition method,” Curr. Appl. Phys. 12 pp.434-436, 2012.
    [5] T. Marron, S. Takashima, Z. Li, and T. P. Chow, “Impact of annealing on Al2O3 gate dielectric for GaN MOS devices,” Phys. Stat. Sol. C, vol. 9, no. 3-4, pp. 907-910, Mar. 2012.
    [6] H. Zhou, G. I. Ng, Z. H. Liu, and S. Arulkumaran, “Improved device performance by post-oxide annealing in atomic-layer-deposited Al2O3/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor on Si,” Appl. Phys. Exp., vol. 4, no. 10, pp. 104102-1- 104102-3, Oct. 2011.
    [7] N. Ikeda, R. Tamura, T. Kokawa, H. Kambayashi, Y. Sato, T. Nomura, and S. Kato, “Over 1.7 kV normally-off GaN hybrid MOS-HFETs with a lower on-resistance on a Si substrate,” in Proc. ISPSD, pp. 284-287, May 2011.
    [8] C. Y. Tsai, T. L. Wu, and A. Chin, “High-performance GaN MOSFET with high-k LaAlO3/SiO2 gate dielectric,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 35-37, Jan. 2012.
    [9] B. R. Park, J. G. Lee, W. Choi, H. Kim, K. S. Seo, and H. Y. Cha, “High-quality ICPCVD SiO2 for normally off AlGaN/GaN-on-Si recessed MOSHFETs,” IEEE Electron Device Lett., vol. 34, no. 3, pp. 354-356, Mar. 2013.

    [10] W. Choi, H. Ryu, N. Jeon, M. Lee, N. H. Lee, K. S. Seo, and H. Y. Cha, “Impacts of conduction band offset and border traps on Vth instability of gate recessed normally-off GaN MISHEMTs, ” ISPSD, pp. 370-373, Jun. 2014.
    [11] W. Choi, O. Seok, H. Ryu, H.-Y. Cha, and K.-S. Seo, “High-voltage and low-leakage-current gate recessed normally-off GaN MIS-HEMTs with dual gate insulator employing PEALD-SiNx /RF-sputtered-HfO2 ,” IEEE Electron Device Lett., vol. 35, no. 2, pp. 175-177, Feb. 2014.
    [12] K. W. Kim, S. D. Jung, D. S. Kim, H. S. Kang, K. S. Im, J. J. Oh, J. B. Ha, J. K. Shin, and J. H. Lee, “Effect of TMAH treatment on device performance of normally off Al2O3/GaN MOSFET,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1376-1378, Oct. 2011.
    [13] Y. Wang, M. Wang, B. Xie, C. P. Wen, J. Wang, Y. Hao, W. Wu, K. J. Chen, and B. Shen, “High-performance normally-off Al2O3/GaN MOSFET using a wet etching-based gate recess technique,” IEEE Electron Device Lett., vol. 34, no. 11, pp. 1370-1372, Nov. 2013.
    [14] M. Wang, Y. Wang, C. Zhang, B. Xie, C. P. Wen, J. Wang, Y. Hao, W. Wu, K. J. Chen, and B. Shen, “900 V/1.6 mΩ· cm2 normally off Al2O3/GaN MOSFET on silicon substrate,” IEEE Trans. Electron Devices, vol. 61, no. 6, pp. 2035-2040, Jun. 2014.
    [15] S. Liu, S. Yang, Z. Tang, Q. Jiang, C. Liu, M. Wang, and K. J. Chen, “Performance enhancement of normally-off Al2O3/AlN/GaN MOS-channel-HEMTs with an ALD-grown AlN interfacial layer,” ISPSD, pp. 362-365, Jun. 2014.
    [16] H. Otake, K. Chikamatsu, A. Yamaguchi, T. Fujishima, and H. Ohta, “Vertical GaN-based trench gate metal oxide semiconductor field-effect transistors on GaN bulk substrates,” Appl. Phys. Exp., vol. 1, no. 1,art. no. 011105, pp. 1-3, 2008.
    [17] M. Okada, Y. Saitoh, M. Yokoyama, K. Nakata, S. Yaegassi, K. Katayama, M. Ueno, M. Kiyama, T. Katsuyama, and T. Nakamura, “Novel vertical heterojunction field-effect transistors with re-grown AlGaN/GaN two-dimensional electron gas channels on GaN substrates,” Appl. Phys. Exp., vol. 3, no. 5, art. no. 054201, pp. 1-3, 2010.
    [18] T. Oka, Y. Ueno, T. Ina, and K. Hasegawa, “Vertical GaN-based trench metal oxide semiconductor field–effect transistors on a freestanding GaN substrate with blocking voltage of 1.6 kV,” Appl. Phys. Exp., vol. 7, no. 2, art. no. 021002, pp. 1-3, 2014.
    [19] H. Nie, Q. Diduck, B. Alvarez, A. P. Edwards, B. M. Kayes, M. Zhang, G. Ye, T. Prunty, D. Bour, and I. C. Kizilyalli, “1.5-kV and 2.2-mΩ-cm2 vertical GaN transistors on bulk-GaN substrates,” IEEE Electron Device Lett., vol. 35, no. 9, pp. 939-941, Sept. 2014.
    [20] http://accuratus.com/alumox.html
    [21] http://accuratus.com/fused.html
    [22] E.A. Alias, N. Zainal, A. Shuhaimi, and Z. Hassan, “Thermal annealing effects on the properties of MBE-GaN p-n junction,” Journal of Physical Science, vol.26(1), pp.35-42, 2015.

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