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研究生: 胡詠峻
Hu, Yung-Chun
論文名稱: 機率性布林邏輯電路的能量最佳化及其應用
Energy Optimization for Probabilistic Boolean Logic Circuits and its Applications
指導教授: 王俊堯
Wang, Chun-Yao
口試委員: 林榮彬
黃婷婷
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 39
中文關鍵詞: 邏輯合成能量最佳化機率性電路
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  • 摘要
    傳統上,我們希望一個電路能夠完全執行正確,沒有任何錯誤發生。然而,對於一些可容忍錯誤的應用,如:影像處理,100%的正確性也許不是必需的。一項有趣的研究指出,如果可以不追求100%的正確性,則可以在能量消耗上獲得大量的好處,此種電路稱為機率性布林邏輯電路。近年來,機率性布林邏輯電路已被提出,然而,並沒有人任何的能量最佳化的演算法被提出來。因此在這篇論文中我們提出了一些策略結合之前的正確性分析而成針對機率性布林電路的能量最佳化演算法。實驗結果顯示在正確性是90%的限制底下,在IWLS2005的測資上可以達到平均31.67%的功率-延遲乘積。最後我們也示範了一些實際上的應用。


    中文摘要 i Abstract ii 誌謝辭 iii Contents iv List of Tables vi List of Figures vii 1 Introduction 1 2 Preliminaries 5 2.1 Probabilistic CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Probabilistic Boolean Logic (PBL) . . . . . . . . . . . . . . . . . . . 8 3 Power Optimization 11 3.1 Level-based Replacement Strategy . . . . . . . . . . . . . . . . . . . . 12 3.2 Testability-based Replacement Strategy . . . . . . . . . . . . . . . . . 13 3.3 PO-aware Testability-based Replacement Strategy . . . . . . . . . . . 15 4 Experimental Results 20 5 Applications 28 5.1 32-bit Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 Image Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Edge Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Conclusion 36

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