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研究生： 楊昌達
Yang, Chang-Ta
論文名稱： 整合金屬閘極與高介電係數材料以改善靜態隨機存取記憶體單元胞穩定度之研究
Integration of Metal Gate Electrode and High-K Gate dielectric for Improved SRAM Unit Cell Stability
指導教授： 張廖貴術
Chang-Liao, Kuei-Shu
口試委員:
學位類別： 博士
Doctor
系所名稱： 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 112
中文關鍵詞： 整合 、金屬閘 、高介電係數 、靜態隨機存取記憶體 、穩定度
外文關鍵詞： Integration, Metal Gate, High-K, SRAM, Stability
相關次數： 點閱：3  下載：0 
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    • 為了持續改善元件的性能，元件的尺寸被要求越來越小，一些新穎的元件已經被提出，例如全空乏絕緣層上覆矽和對稱型雙閘極電晶體。具有中間能階工函數的金屬閘電極HfxTaySizN已經發展出具有優異的熱穩定度。更進一步研究發現，Hf0.19Ta0.41Si0.26N0.14 金屬閘電極展現出了良好的電性如遲滯效應、介面捕獲電荷密度、壓力誘發型漏電流和絕佳的熱穩定度。
    本論文研究的重點同時放在高介電值介電層和金屬閘極的材料選擇上。我們也研究出HfTaN閘電極應用在SiO2和HfOxNy介電層上顯示出令人滿意的熱穩定度。二次離子質譜儀(SIMS)結果發現，相較於在氮氧化鉿閘極介電層，鉿和鉭的擴散深度在二氧化矽中顯示比較不明顯。在電性上，相較於氮氧化鉿閘極介電層，二氧化矽閘極介電層具有比較好的表現例如漏電流、遲滯效應、介面捕獲電荷密度、平帶電壓變化量。隨著金屬化後之退火處理的溫度增加，二氧化矽閘極介電層所形成的元件特性，也仍然具有良好的電性和熱穩定度。
    隨著製程技術不斷的微縮，靜態隨機存取記憶體(SRAM)的穩定度在單位晶胞的設計上顯得相對重要。靜態雜訊邊界(Static Noise Margin, SNM)可視作靜態隨機存取記憶體穩定度預測的一個指標。本論文提供了一個新的方法來預測靜態隨機存取記憶體的穩定度和特性。針對HfTaN閘電極應用在SiO2和HfOxNy介電層上，我們順著新提出的方法，來驗證靜態隨機存取記憶體的穩定度和預測電性。結果發現，高介電值介電層和金屬閘極的材料選擇上是有利於靜態隨機存取記憶體的應用發展。研究結果同時也顯示這觀念同時也適用於深次微米以及奈米級的領域。

    To continuously improve device performance with the shrinkage of device dimension, some novel devices like the fully-depleted silicon-on-insulator (FD-SOI) and symmetric double gate (SDG) transistor have been proposed. Various HfxTaySizN metal gate electrodes were developed to achieve work function near the mid-gap and excellent thermal stability. Furthermore, Hf0.19Ta0.41Si0.26N0.14, demonstrated excellent electrical performances in hysteresis effect, interface trap density, stress-induced leakage current and excellent thermal stability as well.
    The characteristics of integration of high-k gate dielectric and metal gate electrode are also studied. Interaction of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO2 gate dielectric and HfxTayN metal gate shows satisfactory thermal stability. Secondary ion mass spectroscopy (SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO2 gate dielectric than that in HfOxNy. Compared to HfOxNy gate dielectric, SiO2 shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flatband voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO2 gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.
    As the process technology continues to scale, the stability of SRAM is a growing concern in the cell design. Static noise margin (SNM) can serve as a figure of merit in stability evaluation of SRAM cells. A new methodology is proposed to evaluate SRAM cell stability and cell performance to optimize cell design. The sensitivity of SRAM static noise margin and write margin are also studied based on metal gate “HfTaN” with different gate dielectric layer “SiO2” and “HfOxNy” process to develop an SRAM cell stability fault model concept and evaluate SRAM performance. Application of high-k and metal gate is profitable for SRAM application. This result is helpful for usage of high-k and metal gate stacks in sub-45nm and behind.

    Contents Abstract ……………………………………………………………..…….. I 摘要 ………………………………………………………………..………. III Acknowledgment ………………………………………………………….. IV Contents …………………………………………………………………… V Table Captions ……………………………………………………………. VIII Figure Captions …………………………………………………………… IX Chapter 1 Introduction __________________________________________________ 1 1.1 High-k Gate Dielectric …………………………………………………… 1 1.1.1 Why use high-k gate dielectric layer 1.1.2 Some promising gate dielectric layers with high-k gate dielectric 1.2 Metal gate electrode …………………………………………………….. 3 1.2.1 Recent study of metal gate electrode 1.2.2 Motivation to study the metal gate electrode 1.2.3 Challenges of High-k dielectric and metal gate electrode 1.3 SRAM introduction and motivation …………………………………….. 5 1.3.1 Moore’s Law 1.3.2 SRAM Design Tradeoffs 1.3.3 Area and Stability 1.3.4 Review of contemporary SRAM bit cell design methodology 1.3.5 Motivation to study SRAM with High-k metal gate stack 1.3.6 Relationship between threshold voltage and work function 1.3.7 Cell stability with work function 1.3.8 Variation with cell stability 1.3.9 The Monte-Carlo simulation for SRAM application 1.4 Outline of this thesis …………………………………………………… 12 Chapter 2 Experiment and Simulation Details ______________________________ 16 2.1 Manufacturing process flow of MOS capacitor with metal gate electrode HfxTaySizN ………………………………………………………………… 16 2.1.1 Laser Mark and zero layer exposure 2.1.2 Definition of active region 2.1.3 Thermal oxidation of SiO2 gate dielectric 2.1.4 Deposition metal gate electrode HfTaSiN 2.2 Manufacturing process flow of MOS capacitor with metal gate electrode HfTaN and gate dielectric HfOxNy or SiO2 ……………………………………………. 18 2.2.1 Laser Mark and zero layer exposure 2.2.2 Define active region 2.2.3 Thermal oxidation of dielectric SiO2 layer 2.2.4 Deposition of metal gate electrode HfTaN 2.3 Electrical property measurement of MOS capacitor …………………….. 19 2.3.2 Measurement of Hysteresis effect 2.3.3 Measurement of Stress-Induced Leakage Current (SILC) 2.3.4 Extraction of Work Function for metal gate 2.3.5 Interface Trap Density, (Dit) 2.4 Physical characteristics and material analysis of MOS Capacitors ………. 22 2.4.1 X-ray Diffractometer 2.4.2 Secondary Ion Mass Spectrometer (SIMS) 2.5 SRAM performance simulation by hspice simulator ……………………. 23 2.6 Simulation work for work function option ………………………………. 24 Chapter 3 Electrical Characteristics and Thermal Stability of HfxTaySizN Metal Gate Electrode for Advanced MOS Devices _____________________________ 29 3.1 Introduction ………………………………………………………………. 29 3.2 Experimental ……………………………………………………………… 30 3.3 Results and Discussion …………………………………………………… 31 3.3.1 Effects of various Hf compositions in HfTaSiN 3.3.2 Thermal stability of HfxTaySizN gate electrodes 3.4 Conclusions ………………………………………………………………. 35 Chapter 4 Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications _______________________________________ 48 4.1 Introduction ……………………………………………………………… 48 4.2. Experimental ……………………………………………………………. 49 4.3 Results and discussion …………………………………………………… 51 4.4 Conclusion ………………………………………………………………. 53 Chapter 5 Characteristics and cell stability of SRAM _________________________ 59 5.1 Introduction -SRAM functional operation diagram ……………………... 59 5.1.1 SRAM Architecture and schematic 5.1.2 SRAM bitcell performance 5.1.2.1 Read Operation 5.1.2.2 Write operation 5.1.3 SRAM bitcell characteristics and key parameters 5.1.3.1 Cell current 5.1.3.2 Standby current 5.1.3.3 Bitline loading 5.1.4 SRAM Cell Stability 5.1.4.1 Read Stability 5.1.4.2 Write Ability 5.1.5 Statistical Analysis of SRAM Cell Stability 5.2 Vccmin definition and methodology to estimate Vccmin ……………….. 65 5.2.1 Vccmin definition 5.2.2 Vccmin simulation methodology 5.2.3 Simulation condition and Solution approach 5.2.4 SRAM characteristics simulation flow 5.2.5 Variability and performance 5.2.6 Basic criteria for corner simulation 5.3 SRAM cell performance based on high-k and metal gate ……………….. 68 5.3.1 Background introduction 5.3.2 Simulation methodology and experimental conditions 5.3.2.1 Design of experiments for high-k and metal gate stack 5.3.3 SRAM characteristics with HfOxNy gate dielectric and Hf0.27Ta0.58N0.15 5.4. High-k and metal gate usage on characteristics of SRAM ………………. 71 5.5 Summary …………………………………………………………………. 74 Chapter 6 Conclusions ___________________________________________________ 96 6.1 Conclusions of high-k and metal gate …………………………..……… 96 6.2 Suggestions on Future Work ……………………………………………... 97 Reference_____________________________________________________ 99 Publication Lists of Chang-Ta Yang_______________________________ 111

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